公开(公告)号：US20040061168A1

公开(公告)日：2004-04-01

申请号：US10606164

申请日：2003-06-25

Applicant: STMICROELECTRONICS S.r.I

Inventor： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

IPC: H01L029/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract translation: 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。

公开(公告)号：US20020140047A1

公开(公告)日：2002-10-03

申请号：US10158424

申请日：2002-05-29

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Giuseppe Cappelletti ,  Alfonso Maurelli

IPC: H01L021/336 ,  H01L029/00 ,  H01L029/792

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括低工作电压，高性能逻辑电路和具有高于逻辑电路的低工作电压的高工作电压的嵌入​​式存储器件，其提供：在半导体的第一部分上 衬底，形成用于在高工作电压下工作的第一晶体管的第一栅氧化层; 在所述半导体衬底的第二部分上形成用于所述存储器件的存储器单元的第二栅氧化层; 在第一和第二栅氧化层上形成第一晶体管的第一多晶硅层栅电极和用于存储单元的浮栅电极; 在存储单元的浮栅电极上形成介电层; 在半导体衬底的第三部分上形成用于在低工作电压下工作的第二晶体管的第三栅极氧化层; 在所述电介质层和所述半导体衬底的所述第三部分上，从第二多晶硅层形成用于所述存储单元的控制栅电极和用于所述第二晶体管的栅电极; 在半导体衬底的第一部分中，形成用于第一晶体管的源区和漏区; 在半导体衬底的第二部分中，形成用于存储单元的源区和漏区; 在半导体衬底的第三部分中，形成用于第二晶体管的源区和漏极区。

公开(公告)号：US20020119616A1

公开(公告)日：2002-08-29

申请号：US10123507

申请日：2002-04-15

Applicant: STMicroelectronics S.r.I.

Inventor： Livio Baldi ,  Alfonso Maurelli

IPC: H01L021/8234 ,  H01L021/8244

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.

公开(公告)号：US20040268275A1

公开(公告)日：2004-12-30

申请号：US10850834

申请日：2004-05-21

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Cappelletti ,  Alfonso Maurelli

IPC: H01L021/44 ,  G06F017/50

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.

Abstract translation: 测试芯片执行测量以评估互连的性能。 特别地，测量统计失效分布，电迁移和漏电流。 算法检测任何可用的n个金属层的通孔故障。 测试芯片包括ROM存储器阵列。 要测量的通孔在阵列的列中形成。 通过强制通过阵列列和参考列的预定电流来检测通过或接触故障。 通过比较所得的电压降来获得故障分析。

公开(公告)号：US20030032244A1

公开(公告)日：2003-02-13

申请号：US10261987

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Daniela Peschiaroli ,  Alfonso Maurelli ,  Elisabetta Palumbo ,  Fausto Piazza

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.