公开(公告)号：US20020040995A1

公开(公告)日：2002-04-11

申请号：US09960254

申请日：2001-09-20

Applicant: STMicroelectronics S.r.I.

Inventor： Nicola Zatelli ,  Massimo Atti ,  Elisabetta Palumbo ,  Cosimo Torelli

IPC: H01L029/76 ,  H01L029/94

CPC classification number: H01L29/41725 ,  H01L29/7835

Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract translation: 一种具有漏极区域的横向DMOS晶体管，其包括漏电极接触的高浓度部分和由沟道区域限定的低浓度部分。 除了常规的源极，漏极，体和栅电极之外，晶体管还具有与漏极区域的靠近沟道的低浓度部分的点接触的附加电极。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可以用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。

公开(公告)号：US20040152267A1

公开(公告)日：2004-08-05

申请号：US10715887

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I.

Inventor： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection transistor and of the selection transistor, the second band being effective to define the gate region of the floating gate transistor, a portion of the first band further extending on the portion of insulating layer which is adjacent to the byte selection transistor, forming an opening in the portion up to expose the first polysilicon layer, forming a conductive layer in the opening to put said first polysilicon layer in electric contact with said second polysilicon layer.

Abstract translation: 一种用于制造用于集成在半导体衬底上的行和列组织的非易失性存储器单元的矩阵的字节选择晶体管的处理，每个存储单元包括浮置栅晶体管和选择晶体管，该过程提供以下步骤： 相同的半导体衬底用于字节选择晶体管的相应有效区域，用于浮置栅极晶体管和用于分离绝缘层的选择晶体管; 沉积包括至少栅极氧化物层，第一多晶硅层，整个衬底上的电介质层和第二多晶硅层的多层结构，其特征在于其包括以下步骤：通过传统的光刻技术去除形成的多层结构 至少两个条带基本上以并行方式发展到存储器单元矩阵的列，第一条带有效地限定字节选择晶体管和选择晶体管的栅极区域，第二条带有效地 限定浮栅晶体管的栅极区，第一带的一部分在绝缘层的与字节选择晶体管相邻的部分上进一步延伸，在该部分中形成开口以暴露第一多晶硅层，形成导电 以使所述第一多晶硅层与所述第二多晶硅层电接触。

公开(公告)号：US20030032244A1

公开(公告)日：2003-02-13

申请号：US10261987

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Daniela Peschiaroli ,  Alfonso Maurelli ,  Elisabetta Palumbo ,  Fausto Piazza

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.