公开(公告)号：US08791727B2

公开(公告)日：2014-07-29

申请号：US13907468

申请日：2013-05-31

Applicant: STMicroelectronics S.r.I.

Inventor： Valeria Bottarel ,  Giulio Ricotti ,  Fabio Quaglia

IPC: H03K3/00 ,  H03B1/00

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.

Abstract translation: 低压隔离开关适合于从连接节点接收高电压信号，并通过连接端将所述高电压信号发送到负载。 隔离开关包括连接在第一和第二参考电极之间的驱动块，并且包括耦合在第一电压基准（Vss）和第一驱动电路节点之间的第一驱动晶体管和耦合在驱动电路节点和第二驱动电路节点之间的第二驱动晶体管 电源参考电压。 开关包括连接到连接端子（pzt）的隔离块，连接节点和驱动中心电路节点，并且包括电压限制器块，二极管块和控制晶体管。 控制晶体管连接在连接节点和连接端子之间的二极管块两端，并具有连接到驱动中心电路节点的控制端子。

公开(公告)号：US20230006546A1

公开(公告)日：2023-01-05

申请号：US17364147

申请日：2021-06-30

Applicant: STMicroelectronics S.r.I.

Inventor： Juri Giovannone ,  Valeria Bottarel ,  Stefano Corona

IPC: H02M3/04 ,  H03K5/24

Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.