公开(公告)号：US20230353052A1

公开(公告)日：2023-11-02

申请号：US18300945

申请日：2023-04-14

Applicant: STMicroelectronics S.r.l

Inventor： Alessandro Nicolosi ,  Alessandra Farina ,  Edoardo Bonizzoni

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/08

CPC classification number: H02M3/158 ,  H02M1/0009 ,  H02M1/083

Abstract: A control module, for a resonant switched-capacitor converter with an inductor, includes a controller stage, an input stage generating a control signal indicating a control quantity, a delay stage generating a duration signal indicating a time quantity, and a circuit indicating zero crossings of the inductor current. If the control quantity is variable, the input stage clamps the control quantity to a control threshold. When in normal mode, the controller stage controls the converter to carry out a phase sequence with timings that depend on the zero crossings and the time quantity, so the converter generates an output current that depends on the time quantity and is prevented from dropping below a minimum current. If the output voltage reaches an upper threshold, the controller stage switches into pulse-skipping mode to suspend the phase sequence, and resumes the phase sequence after the output voltage drops to a lower threshold.

公开(公告)号：US20230327555A1

公开(公告)日：2023-10-12

申请号：US18295538

申请日：2023-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Nicolosi ,  Alessandra Farina ,  Edoardo Bonizzoni

IPC: H02M3/158 ,  H02M3/07 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M3/07 ,  H02M1/0025

Abstract: A control module, for a resonant switched-capacitor converter having first, second, third and fourth cascaded switches and generating an output voltage, includes a timing circuit generating a clock, a controller generating first and second control signals indicating, respectively, first and second control quantities, the difference between which being a function of the difference between a reference quantity and a feedback quantity depending on the output voltage, first and second delay circuits that generate first and second logic signals and, respectively, third and fourth logic signals, the first and third logic signals being delayed with respect to the clock as a function of, respectively, the first and second control quantities, the second and fourth control signals being respectively the logic negation of the first and third logic signals, and a driver that controls the first, second, third, and fourth switches based on, respectively, the first, second, third, and fourth logic signals.