公开(公告)号：US20030227037A1

公开(公告)日：2003-12-11

申请号：US10394422

申请日：2003-03-21

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Moscatelli ,  Giuseppe Croce

IPC: H01L029/76

CPC classification number: H01L21/823814 ,  H01L21/823835 ,  H01L21/823857

Abstract: A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Abstract translation: 一种集成到半导体材料芯片中的MOS晶体管的制造方法，包括从芯片的内部延伸到芯片的表面的第一和第二有源区。 该方法包括以下步骤：a）在芯片的表面上形成绝缘材料层，并在所述绝缘层上沉积一层导电材料，b）限定晶体管的绝缘栅电极，从所述叠加的绝缘导电 层，c）从所述叠加的绝缘和导电层限定布置在第一有源区的第一表面部分上的附加结构，以及d）在绝缘栅极和附加结构之间放置放置在第二表面上的介电隔离物 第一活性区域的部分。

公开(公告)号：US20040229438A1

公开(公告)日：2004-11-18

申请号：US10746881

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Moscatelli ,  Claudia Raffaglio ,  Alessandra Merlini ,  M. P. Galbiati

IPC: H01L021/8234

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66659 ,  H01L29/7835

Abstract: A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors. The gate region of the vertical or lateral transistors is then covered with a protective layer. A low-resistance layer is then formed on the gate regions of the CMOS transistors.

Abstract translation: 公开了一种在公共半导体衬底上分别在衬底的至少第一和第二部分上形成CMOS晶体管和垂直或横向MOS晶体管的工艺。 在基板上形成第一电介质层。 在第一部分中，在第一介电层上形成第一半导体材料层。 然后在衬底上形成包括第二电介质层，第二半导体层和低电阻层的堆叠结构。 第一端口被限定在第二半导体层和低电阻层中，以提供垂直或横向MOS晶体管的栅极区域。 然后通过使用第二介电层作为屏幕，从基板的第一部分去除第二半导体层和低电阻层。 然后限定第二介电层和第二半导体层中的第二端口以为CMOS晶体管提供栅极区域。 然后用保护层覆盖垂直或横向晶体管的栅极区域。 然后在CMOS晶体管的栅极区域上形成低电阻层。

公开(公告)号：US20040104777A1

公开(公告)日：2004-06-03

申请号：US10723705

申请日：2003-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno Murari ,  Alessandro Moscatelli ,  Lorenzo Labate

IPC: H03F001/22

CPC classification number: H03F1/223

Abstract: A power amplifier comprising at least a load element and at least an active element inserted, in series to each other, between a first and a second voltage reference is described. Advantageously, according to an embodiment of the invention, the load element comprises a DMOS transistor.

Abstract translation: 描述了功率放大器，其至少包括负载元件和在第一和第二参考电压之间彼此串联插入的至少一个有源元件。 有利地，根据本发明的实施例，负载元件包括DMOS晶体管。

公开(公告)号：US20010048133A1

公开(公告)日：2001-12-06

申请号：US09862750

申请日：2001-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe Croce ,  Alessandro Moscatelli ,  Alessandra Merlini ,  Paola Galbiati

IPC: H01L029/76 ,  H01L029/94

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract translation: LDMOS结构形成在半导体衬底的第一导电类型的区域中，并且包括栅极，漏极区域和源极区域。 源极区域由第一区域内的第二导电类型的体扩散形成，并且第一类型的导电性的源极扩散在体扩散内。 第二类导电性的电连接扩散是源极区域的有限区域，并且延伸穿过源极扩散并且向下延伸到身体扩散。 源扩散和电连接扩散至少有一个源触点。 LDMOS结构还包括在源极区域的整个区域上的硅化物层，使源扩散和电连接扩散短路。 源极接触形成在硅化物层上。

公开(公告)号：US20020011626A1

公开(公告)日：2002-01-31

申请号：US09839596

申请日：2001-04-20

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe Croce ,  Alessandro Moscatelli ,  Alessandra Merlini ,  Paola Galbiati

IPC: H01L029/76

CPC classification number: H01L29/0878 ,  H01L29/7816

Abstract: A reduced surface field (RESURF) lateral diffused metal oxide semiconductor (LDMOS) integrated circuit includes a first region having a first conductivity type defined in a semiconductor substrate having a second conductivity type, a body region having the second conductivity type in the first region, and a source region having the first conductivity type formed in the body region. More specifically, the body region may be within a surface portion of the first region that is more heavily doped than the remainder of the of the first region.

Abstract translation: 减少的表面场（RESURF）横向扩散金属氧化物半导体（LDMOS）集成电路包括具有第一导电类型的第一区域，其具有限定在具有第二导电类型的半导体衬底中，在第一区域具有第二导电类型的体区， 以及形成在身体区域中的具有第一导电类型的源极区域。 更具体地，身体区域可以在比第一区域的其余部分更重掺杂的第一区域的表面部分内。