System and method for clock resynchronization

    公开(公告)号:US11962677B2

    公开(公告)日:2024-04-16

    申请号:US17720087

    申请日:2022-04-13

    CPC classification number: H04L7/0331 H03L7/06 H04L7/0016 H04L7/0054 H04L7/0079

    Abstract: A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

    SYSTEM AND METHOD FOR CLOCK RESYNCHRONIZATION

    公开(公告)号:US20230336325A1

    公开(公告)日:2023-10-19

    申请号:US17720087

    申请日:2022-04-13

    CPC classification number: H04L7/0331 H03L7/06

    Abstract: A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

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