Process for forming a buried cavity in a semiconductor material wafer and a buried cavity
    1.
    发明申请
    Process for forming a buried cavity in a semiconductor material wafer and a buried cavity 有权
    在半导体材料晶片和掩埋腔中形成掩埋腔的工艺

    公开(公告)号:US20040106290A1

    公开(公告)日:2004-06-03

    申请号:US10712211

    申请日:2003-11-12

    CPC classification number: B81C1/00404

    Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45null with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

    Abstract translation: 该方法包括以下步骤:在半导体材料晶片的顶部上形成具有格子结构的孔掩模,并且包括多个开口,每个开口具有大致正方形的形状,并且相对于平面的平面倾斜45° 晶圆; 在晶片的TMAH中进行各向异性蚀刻,使用所述带孔掩模,从而形成空腔,其横截面具有倒立的等腰梯形的形状; 并且使用TEOS进行化学气相沉积,由此形成TEOS层,其完全封闭了孔罩的开口,并且限定了覆盖在空腔上的隔膜,并且随后可以制造悬浮的一体结构。

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