公开(公告)号：US20040106290A1

公开(公告)日：2004-06-03

申请号：US10712211

申请日：2003-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

IPC: H01L021/302 ,  H01L021/461

CPC classification number: B81C1/00404

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45null with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

Abstract translation: 该方法包括以下步骤：在半导体材料晶片的顶部上形成具有格子结构的孔掩模，并且包括多个开口，每个开口具有大致正方形的形状，并且相对于平面的平面倾斜45° 晶圆; 在晶片的TMAH中进行各向异性蚀刻，使用所述带孔掩模，从而形成空腔，其横截面具有倒立的等腰梯形的形状; 并且使用TEOS进行化学气相沉积，由此形成TEOS层，其完全封闭了孔罩的开口，并且限定了覆盖在空腔上的隔膜，并且随后可以制造悬浮的一体结构。

公开(公告)号：US20020014678A1

公开(公告)日：2002-02-07

申请号：US09899573

申请日：2001-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： Pietro Erratico

IPC: H01L021/331 ,  H01L029/00

CPC classification number: H01L29/7816 ,  H01L21/762 ,  H01L21/822 ,  H01L27/0248

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract translation: 形成在半导体芯片上的集成结构包括具有第一导电类型的衬底和在衬底上生长的外延层。 外延层可以具有第一导电类型以及小于衬底的导电性的导电性。 此外，集成结构可以包括外延层中的第一区域和第二区域，每个具有与外延层相反的导电类型。 第一和第二区域可以从与衬底相对的外延层的表面延伸到外延层中以与其形成相应的第一和第二结。 此外，该集成结构还可以包括隔离元件，用于当第一结被直接偏置时，减少从第一区到第二区的注入通过外延层的电流。