公开(公告)号：US20020149089A1

公开(公告)日：2002-10-17

申请号：US10035006

申请日：2001-12-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Loris Vendrame ,  Paolo Caprara ,  Giorgio Oddone ,  Antonio Barcella

IPC: H01L029/00

CPC classification number: H01L29/7322 ,  H01L29/0813

Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (Pnull) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (Nnull) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (Pnull) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).

Abstract translation: 晶体管包括在相同类型（P）导电性的半导体材料层中具有导电性的第一类型（P）的衬底区域（14），至少第一类型（P +）的第一接触区域（13） 在衬底区域（14）内并且与晶体管的第一端子（C）相邻的导电性，位于衬底区域（14）内部的第二类型（N）导电体的阱（11），其中阱（11） 第二类型（N）的导电性包括与晶体管的第二端子（B）的区域相邻的至少第二导电类型（N +）的第二接触区域（12）和多个第三接触区域（10） ）通过适当的绝缘形状（20）与每个（10）和另一个（12）插入的晶体管的第三端子（E1，...，E3）的多个区域相邻的第一类型的导电性（P +）） 。

公开(公告)号：US20040188759A1

公开(公告)日：2004-09-30

申请号：US10745295

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Valentina Tessa Contin ,  Carlo Caimi ,  Davide Merlani ,  Paolo Caprara

IPC: H01L029/76

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11524 ,  H01L27/11534

Abstract: An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.

Abstract translation: MOS器件具有覆盖堆叠的堆叠层和钝化层。 堆叠由第一多晶硅区域和由彼此顶部布置并由中间介电区域隔开的第二多晶硅区域形成。 由基本上没有台阶的柱结构形成的电连接区域延伸穿过钝化层，第二多晶硅区域和中间介电区域，并且终止于与第一多晶硅区域接触，从而使第一多晶硅区域和 第二多晶硅区域。 电连接区域的制造仅需要一个掩模。