公开(公告)号：US20040188759A1

公开(公告)日：2004-09-30

申请号：US10745295

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Valentina Tessa Contin ,  Carlo Caimi ,  Davide Merlani ,  Paolo Caprara

IPC: H01L029/76

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11524 ,  H01L27/11534

Abstract: An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.

Abstract translation: MOS器件具有覆盖堆叠的堆叠层和钝化层。 堆叠由第一多晶硅区域和由彼此顶部布置并由中间介电区域隔开的第二多晶硅区域形成。 由基本上没有台阶的柱结构形成的电连接区域延伸穿过钝化层，第二多晶硅区域和中间介电区域，并且终止于与第一多晶硅区域接触，从而使第一多晶硅区域和 第二多晶硅区域。 电连接区域的制造仅需要一个掩模。