公开(公告)号：US20210319836A1

公开(公告)日：2021-10-14

申请号：US17224024

申请日：2021-04-06

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Enrico CASTALDO ,  Francesca GRANDE ,  Santi Nunzio Antonino PAGANO ,  Giuseppe NASTASI ,  Franco ITALIANO

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11529

Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.