公开(公告)号：US10985736B2

公开(公告)日：2021-04-20

申请号：US16894640

申请日：2020-06-05

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Daniele Mangano ,  Roland Van Der Tuijn ,  Pasquale Butta′

IPC: H03K3/01 ,  H03K17/20 ,  G06F1/24 ,  H03K19/20

Abstract: An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

公开(公告)号：US11803226B2

公开(公告)日：2023-10-31

申请号：US16874020

申请日：2020-05-14

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Pasquale Butta′ ,  Sergio Abenda

IPC: G06F1/3234 ,  H03K3/037 ,  G06F1/3296

CPC classification number: G06F1/325 ,  G06F1/3243 ,  H03K3/037

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

公开(公告)号：US11025289B2

公开(公告)日：2021-06-01

申请号：US16800793

申请日：2020-02-25

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Pasquale Butta′

IPC: H04B1/40 ,  H02M1/00

Abstract: A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.