公开(公告)号：US20240364319A1

公开(公告)日：2024-10-31

申请号：US18636983

申请日：2024-04-16

Applicant: MONTAGE ELECTRONICS (SHANGHAI) CO., LTD.

Inventor： Pingshun MA ,  Bo QU

IPC: H03K5/13 ,  H03K3/037 ,  H03K5/00

CPC classification number: H03K5/13 ,  H03K3/037 ,  H03K2005/00052

Abstract: The application relates to the field of integrated circuit design and discloses a digital phase interpolator, comprising: a first delay unit, a pre-interpolating unit, a second delay unit, and a phase interpolating unit; wherein each interpolation branch comprises a pre-interpolating unit and a re-interpolating unit. For two input signals with preset phase differences, the digital phase interpolator performs two interpolation processes, one at the pre-interpolating unit and the other at the phase interpolating unit. This distributed quadratic interpolation reduces the task of the phase interpolation unit, helps to reduce the number of stages of the phase interpolating unit, reduces the input load, reduces the overall power consumption and the overall area, ensures the rationality of its own power consumption, and improves the linearity of phase interpolation to some extent.

公开(公告)号：US20240361371A1

公开(公告)日：2024-10-31

申请号：US18767283

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Hsien Tsai ,  Ruey-Bin Sheen ,  Chih-Hsien Chang ,  Cheng-Hsiang Hsieh

IPC: G01R29/02 ,  G01R25/00 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21

CPC classification number: G01R29/023 ,  G01R25/005 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21 ,  H03K2005/00058

Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

公开(公告)号：US20240356555A1

公开(公告)日：2024-10-24

申请号：US18126691

申请日：2023-03-27

Applicant: International Business Machines Corporation

Inventor： John Timmerwilke

IPC: H03K19/195 ,  H03K3/037 ,  H03K19/173 ,  H03K19/21

CPC classification number: H03K19/195 ,  H03K3/037 ,  H03K19/173 ,  H03K19/21

Abstract: A device comprises a clockless single flux quantum (SFQ) logic circuit comprising input and output stages and a configurable logic circuit which comprises at least one configurable logic gate that holds an internal state. The input stage comprises a signal input converter circuit which receives a two-level input signal and generates an SFQ pulse on each rising and falling edge of the two-level input signal. The configurable logic circuit performs logic operations using SFQ pulses from the input stage, and outputs SFQ pulses to the output stage which comprises a signal output converter circuit that converts each output SFQ pulse into a two-level output signal. The signal output converter circuit holds an internal state. The configurable logic circuit is configurable to implement a logic function by initializing the internal state of the signal output converter circuit and/or the internal state of the at least one configurable logic gate.

公开(公告)号：US20240329116A1

公开(公告)日：2024-10-03

申请号：US18349069

申请日：2023-07-07

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog Kyoon JEONG ,  Chan Ho KYE ,  Ji Hee KIM

IPC: G01R31/28 ,  H03K3/037 ,  H03K5/00 ,  H03K19/20

CPC classification number: G01R31/2851 ,  H03K3/037 ,  H03K5/00006 ,  H03K19/20

Abstract: Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission/reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

公开(公告)号：US20240322799A1

公开(公告)日：2024-09-26

申请号：US18240796

申请日：2023-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deep BANERJEE ,  Lokesh Kumar GUPTA ,  Madhulatha BONU

IPC: H03K3/017 ,  H03K3/037 ,  H03K17/56

CPC classification number: H03K3/017 ,  H03K3/037 ,  H03K17/56

Abstract: An analog duty-cycle detector includes: off-time detection circuitry; on-time detection circuitry; compare circuitry; and a controller. The off-time detection circuitry includes a first transistor and a first capacitor. The on-time detection circuitry includes a second transistor and a second capacitor. The compare circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the compare circuitry is coupled to a first terminal of the first capacitor. The second terminal of the compare circuitry is coupled to a first terminal of the second capacitor. The controller has a first terminal and a second terminal. The first terminal of the controller coupled to a control terminal of the first transistor. The second terminal of the controller coupled to the control terminal of the second transistor.

公开(公告)号：US12101611B2

公开(公告)日：2024-09-24

申请号：US17874210

申请日：2022-07-26

Applicant: SYNTIANT

Inventor： Joseph Cordaro ,  David Garrett

IPC: H04R3/00 ,  G06F1/08 ,  G06F1/12 ,  H04R19/04 ,  H03K3/037

CPC classification number: H04R3/005 ,  G06F1/08 ,  G06F1/12 ,  H04R19/04 ,  H03K3/037 ,  H04R2201/003

Abstract: A clocking technique for reducing the power of PDM microphones in dual microphone systems is disclosed. A clock for a conventional PDM microphone (PDMCLK) is provided by another source. PDM microphones send serial data (PDMDAT) on the rising (“Right”) or falling (“Left”) edge of the PDMCLK clock, depending on how the microphone is configured. In a dual PDM microphone configuration, the microphones alternate sending data on the rising edges (transitions to logic-1) and falling edges (transitions to logic-0) of PDMCLK. Typically, Complementary Metal-Oxide-Semiconductor (CMOS) logic is used to transmit or drive the clock signal to the microphones. CMOS drivers consume power primarily when they transition from a logic-0 to a logic-1 or from a logic-1 to a logic-0. Thus, a free-running clock signal will produce the highest CMOS power consumption. In a dual PDM microphone system, it is desirable to operate in a low power mode with a single microphone at times and to operate with the full functionality (and power consumption) of both microphones at other times. In a conventional system, both PDM microphones share both the PDMDAT and PDMCLK signal lines. Thus both microphones must be clocked even if only one is being used. This wastes power in both the PDMCLK output buffer (driving both loads even if one is not being used) as well as in the unused microphone (where all of the clock circuits are active and switching). A novel PDM microphone interface is disclosed that provides a three signal interface comprising a separate PDMCLK signal to each microphone while maintaining a single common PDMDAT line.

公开(公告)号：US12088298B2

公开(公告)日：2024-09-10

申请号：US18042208

申请日：2021-07-23

Applicant: HANGZHOU YUN LED CHIP PHOTOELECTRICITY TECH. CO., LTD.

Inventor： Yinghan Yang ,  Zixun Zhang

IPC: H03K21/00 ,  H03K3/037 ,  H05B45/32

CPC classification number: H03K21/00 ,  H03K3/037 ,  H05B45/32

Abstract: A computing apparatus triggered by an edge of a supply-line signal with a pulse width counter includes: a clock circuit to supply clock signals to a pulse width counter from an output port of said clock circuit; said pulse width counter triggered by said clock signals to count the pulse width of a supply-line signal from a power supply line, to set a circuit status of said computing apparatus in accordance with said pulse width, and to output said circuit status to an edge-triggered computing unit; and the edge-triggered computing unit to do computing triggered by an edge of a supply-line signal, and to output computing result as the output of said computing apparatus in accordance with said circuit status. The circuit status of the computing apparatus is set in accordance with pulse width counter of supply-line signals.

公开(公告)号：US20240297585A1

公开(公告)日：2024-09-05

申请号：US18177276

申请日：2023-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fangli Ge ,  Luyang He ,  Ding Yan

IPC: H02M3/158 ,  H02M1/32 ,  H03K3/037 ,  H03K5/24

CPC classification number: H02M3/1582 ,  H02M1/32 ,  H03K3/037 ,  H03K5/24

Abstract: A voltage converter includes an amplifier, a voltage-to-current (VtoI) converter circuit, a current mirror, a slope generation circuit, and a transistor. The amplifier has an amplifier output. The VtoI converter circuit has a VtoI input and a VtoI output. The VtoI input is coupled to the amplifier output. The current mirror has a current mirror input and a current mirror output. The current mirror input is coupled to the VtoI output. The slope generation circuit has an input coupled to the current mirror input. The transistor is coupled between the amplifier output and a reference terminal. The transistor has a control input coupled to the current mirror output.

公开(公告)号：US20240259005A1

公开(公告)日：2024-08-01

申请号：US18566562

申请日：2022-05-31

Applicant: Nordic Semiconductor ASA

Inventor： Martin KOLLERUD ,  Kyrre GONSHOLT

IPC: H03K5/156 ,  H03K3/037 ,  H03K5/133

CPC classification number: H03K5/1565 ,  H03K3/037 ,  H03K5/133

Abstract: A circuit portion comprises a signal generator, clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions. A circuit sub-portion introduces a delay to the alternating logic signal. An edge-travel detector samples the delayed alternating logic signal and outputs an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal. A mask block compares the edge-travel signal with a mask signal to determine whether the timing of the logic transition matches one or more candidate timings, and outputs a comparison signal in dependence on this determination.

公开(公告)号：US20240250668A1

公开(公告)日：2024-07-25

申请号：US18100975

申请日：2023-01-24

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Umesh Chandra Srivastava ,  Shiv Kumar Vats ,  Manish Sharma

IPC: H03K3/037 ,  G01R31/3185 ,  G01R31/3187 ,  H03K19/20

CPC classification number: H03K3/037 ,  G01R31/318597 ,  G01R31/3187 ,  H03K19/20

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.