公开(公告)号：US20200013901A1

公开(公告)日：2020-01-09

申请号：US16458363

申请日：2019-07-01

Applicant: STMicroelectronics SA

Inventor： Louise De Conti ,  Philippe Galy

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

Abstract: An integrated electronic device, comprising at least one MOS transistor produced in and on an active zone of a silicon-on-insulator substrate, said at least one first transistor including a first gate region and a first substrate contact zone that is surrounded by the first gate region.

公开(公告)号：US11581303B2

公开(公告)日：2023-02-14

申请号：US16869840

申请日：2020-05-08

Applicant: STMicroelectronics SA

Inventor： Louise De Conti ,  Philippe Galy

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

公开(公告)号：US11296072B2

公开(公告)日：2022-04-05

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas Bedecarrats ,  Louise De Conti ,  Philippe Galy

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.

公开(公告)号：US11916061B2

公开(公告)日：2024-02-27

申请号：US18095728

申请日：2023-01-11

Applicant: STMicroelectronics SA

Inventor： Louise De Conti ,  Philippe Galy

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0277 ,  H01L27/1203 ,  H01L29/7436

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

公开(公告)号：US11387354B2

公开(公告)日：2022-07-12

申请号：US16870116

申请日：2020-05-08

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Louise De Conti

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.