公开(公告)号：US11296072B2

公开(公告)日：2022-04-05

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas Bedecarrats ,  Louise De Conti ,  Philippe Galy

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.

公开(公告)号：US10853038B2

公开(公告)日：2020-12-01

申请号：US16157464

申请日：2018-10-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06F7/58 ,  H03K3/012 ,  H03K3/84

Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.

公开(公告)号：US11250309B2

公开(公告)日：2022-02-15

申请号：US15694510

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/04 ,  G06N3/063 ,  H01L27/02 ,  G11C11/54 ,  H01L29/423 ,  H03K3/356

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

公开(公告)号：US20180276526A1

公开(公告)日：2018-09-27

申请号：US15694510

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/04 ,  G06N3/063

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G11C11/54 ,  H01L27/027 ,  H01L27/0285 ,  H01L29/42376 ,  H03K3/356

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

公开(公告)号：US11954589B2

公开(公告)日：2024-04-09

申请号：US17572899

申请日：2022-01-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/065 ,  G11C11/54 ,  H01L27/02 ,  H01L29/423 ,  H03K3/356

CPC classification number: G06N3/065 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  H01L27/027 ,  H01L27/0285 ,  G06N3/04 ,  H01L29/42376 ,  H03K3/356

Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

公开(公告)号：US11450689B2

公开(公告)日：2022-09-20

申请号：US16927510

申请日：2020-07-13

Applicant: STMicroelectronics SA

Inventor： Thomas Bedecarrats ,  Philippe Galy

IPC: H01L27/12

Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

公开(公告)号：US10804275B2

公开(公告)日：2020-10-13

申请号：US16199810

申请日：2018-11-26

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Thomas Bedecarrats ,  Philippe Galy

IPC: H01L27/108 ,  G11C11/39 ,  H01L27/102 ,  H01L29/74 ,  G11C11/402 ,  G11C11/409

Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.

公开(公告)号：US20190114145A1

公开(公告)日：2019-04-18

申请号：US16157464

申请日：2018-10-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06F7/58 ,  H03K3/84 ,  H03K3/012

Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.

公开(公告)号：US20180276536A1

公开(公告)日：2018-09-27

申请号：US15697598

申请日：2017-09-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06N3/049 ,  G06N3/0635 ,  G11C11/54

Abstract: An integrated artificial neuron device includes a refractory circuit configured to inhibit signal integration for an inhibition duration after delivery of an output signal. The refractory circuit includes a first MOS transistor coupled between an input node and a reference node and having a gate connected to the output node by a second MOS transistor having a first electrode coupled to the supply node and a gate coupled to the output node. The refractory circuit further includes a resistive-capacitive circuit coupled between the supply node, the reference node and the gate of the second MOS transistor. An inhibition duration depends on a time constant of the resistive-capacitive circuit.