公开(公告)号：US11138036B2

公开(公告)日：2021-10-05

申请号：US16739388

申请日：2020-01-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Denis ,  Christophe Taba

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/1081 ,  G06F13/364 ,  G06F13/16 ,  G06F13/30 ,  G06F13/40

Abstract: Requests are received by a routing circuit. A plurality of first round-robin arbitration circuits are coupled to the routing circuit. There are as many first round-robin arbitration circuits as there are possible priority levels for the requests. The routing circuit operates to transmit each received request to a number of first round-robin arbitration circuits determined according to the priority level of the request. A second round-robin arbitration circuit has inputs respectively connected to the outputs of the first round-robin arbitration circuits.

公开(公告)号：US11327915B2

公开(公告)日：2022-05-10

申请号：US16830626

申请日：2020-03-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Francois Cloute ,  Christophe Taba

IPC: G06F13/28

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

公开(公告)号：US11755516B2

公开(公告)日：2023-09-12

申请号：US17716481

申请日：2022-04-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Francois Cloute ,  Christophe Taba

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.