公开(公告)号：US20240260275A1

公开(公告)日：2024-08-01

申请号：US18419385

申请日：2024-01-22

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shohei Kamisaka ,  Yosuke Nosho ,  Usha Raghuram ,  Kavita Shah ,  Jie Zhou ,  Iting Lin ,  Eli Harari

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: A fabrication process for a memory structure including three-dimensional arrays of thin-film ferroelectric storage transistors is disclosed. In some embodiments, the ferroelectric storage transistors are organized in three-dimensional arrays of horizontal NOR memory strings. In some embodiments, the fabrication process uses a high aspect-ratio damascene process to form local word line structures that extends through the multiple layers of the three-dimensional memory structure. In particular, the high aspect-ratio local word line damascene process forms the gate stack layers, including the channel layer, the gate dielectric layer and the gate conductor layer, in the same sequence of additive deposition processes without any of the gate stack layers being subjected to any intervening etching process. In this manner, the integrity of the gate stack layers and their interfaces are well preserved and the transistor characteristics of the ferroelectric storage transistors are enhanced.