公开(公告)号：US12096630B2

公开(公告)日：2024-09-17

申请号：US16577469

申请日：2019-09-20

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/30

CPC classification number: H10B43/20 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H10B43/30

Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.

公开(公告)号：US12073082B2

公开(公告)日：2024-08-27

申请号：US18306073

申请日：2023-04-24

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Youn Cheul Kim ,  Richard S. Chernicoff ,  Khandker Nazrul Quader ,  Robert D. Norman ,  Tianhong Yan ,  Sayeef Salahuddin ,  Eli Harari

IPC: G11C11/00 ,  G06F3/06 ,  H01L23/00 ,  H01L25/18

CPC classification number: G06F3/0611 ,  G06F3/0631 ,  H01L24/20 ,  H01L25/18 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1435

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

公开(公告)号：US20240179919A1

公开(公告)日：2024-05-30

申请号：US18436365

申请日：2024-02-08

Applicant: SunRise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/40 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2251 ,  H01L21/31111 ,  H01L21/32053 ,  H01L23/528 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78642 ,  H10B43/10 ,  H10B43/27

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20240161837A1

公开(公告)日：2024-05-16

申请号：US18420073

申请日：2024-01-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/27

CPC classification number: G11C16/3431 ,  G06F17/16 ,  G06N3/063 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/78633 ,  H01L29/7926 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US11844204B2

公开(公告)日：2023-12-12

申请号：US18050937

申请日：2022-10-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L29/66 ,  H10B99/00 ,  H01L29/786 ,  H01L21/3065

CPC classification number: H10B99/00 ,  H01L21/3065 ,  H01L29/6675 ,  H01L29/78642 ,  H01L29/78663 ,  H01L29/78672

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

公开(公告)号：US20230290418A9

公开(公告)日：2023-09-14

申请号：US17934965

申请日：2022-09-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  G06F17/16 ,  G06N3/063

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  H01L29/1037 ,  H01L29/0847 ,  H01L29/78633 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L29/40117 ,  G11C16/0416 ,  G11C16/0491 ,  H01L29/66833 ,  H01L29/7926 ,  G11C16/0466 ,  G06F17/16 ,  G06N3/063 ,  H01L27/11565

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US20230282283A1

公开(公告)日：2023-09-07

申请号：US18175277

申请日：2023-02-27

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/04 ,  H10B51/10 ,  H10B51/20 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51

CPC classification number: G11C16/0483 ,  H10B51/10 ,  H10B51/20 ,  H01L29/7869 ,  H01L29/78391 ,  H01L29/6684 ,  H01L29/516

Abstract: A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The ferroelectric storage transistors are junctionless field-effect transistors having a ferroelectric polarization layer formed adjacent a semiconductor oxide layer as the channel region. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process.

公开(公告)号：US11610914B2

公开(公告)日：2023-03-21

申请号：US17161504

申请日：2021-01-28

Applicant: Sunrise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/04

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US11515432B2

公开(公告)日：2022-11-29

申请号：US17155673

申请日：2021-01-22

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L21/8239 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

公开(公告)号：US20220328518A1

公开(公告)日：2022-10-13

申请号：US17809535

申请日：2022-06-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/308

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.