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公开(公告)号：US20220238536A1
公开(公告)日：2022-07-28
申请号：US17576544
申请日：2022-01-14
IPC分类号： H01L27/1158 , H01L27/11519 , H01L27/11553 , H01L27/11565 , G11C7/18 , G11C8/14
摘要： A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.
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公开(公告)号：US20230247831A9
公开(公告)日：2023-08-03
申请号：US17382126
申请日：2021-07-21
发明人： Vinod Purayath , Yosuke Nosho , Shohei Kamisaka , Michiru Nakane , Eli Harari
IPC分类号： H01L27/11582 , H01L29/51 , H01L21/28
CPC分类号： H01L27/11582 , H01L29/513 , H01L29/40117 , H01L29/518 , H01L29/517
摘要： A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
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公开(公告)号：US20220199532A1
公开(公告)日：2022-06-23
申请号：US17548034
申请日：2021-12-10
发明人： Shohei Kamisaka , Yosuke Nosho
IPC分类号： H01L23/535 , H01L23/528 , H01L23/532 , H01L21/768
摘要： A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.
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公开(公告)号：US20220028886A1
公开(公告)日：2022-01-27
申请号：US17382126
申请日：2021-07-21
发明人： Vinod Purayath , Yosuke Nosho , Shohei Kamisaka , Michiru Nakane , Eli Harari
IPC分类号： H01L27/11582 , H01L29/51 , H01L21/28
摘要： A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
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公开(公告)号：US20240260275A1
公开(公告)日：2024-08-01
申请号：US18419385
申请日：2024-01-22
发明人： Shohei Kamisaka , Yosuke Nosho , Usha Raghuram , Kavita Shah , Jie Zhou , Iting Lin , Eli Harari
摘要： A fabrication process for a memory structure including three-dimensional arrays of thin-film ferroelectric storage transistors is disclosed. In some embodiments, the ferroelectric storage transistors are organized in three-dimensional arrays of horizontal NOR memory strings. In some embodiments, the fabrication process uses a high aspect-ratio damascene process to form local word line structures that extends through the multiple layers of the three-dimensional memory structure. In particular, the high aspect-ratio local word line damascene process forms the gate stack layers, including the channel layer, the gate dielectric layer and the gate conductor layer, in the same sequence of additive deposition processes without any of the gate stack layers being subjected to any intervening etching process. In this manner, the integrity of the gate stack layers and their interfaces are well preserved and the transistor characteristics of the ferroelectric storage transistors are enhanced.
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公开(公告)号：US11751391B2
公开(公告)日：2023-09-05
申请号：US17382126
申请日：2021-07-21
发明人： Vinod Purayath , Yosuke Nosho , Shohei Kamisaka , Michiru Nakane , Eli Harari
CPC分类号： H10B43/27 , H01L29/40117 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
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公开(公告)号：US20220231040A1
公开(公告)日：2022-07-21
申请号：US17559101
申请日：2021-12-22
发明人： Vinod Purayath , Kenta Ohama , Yosuke Nosho
IPC分类号： H01L27/11578 , H01L27/11573
摘要： A VNOR memory string includes: (a) first and second pillars embedded in multiple composite layers, each composite layer comprising an insulator layer and a conductor layer, the first and second pillars each comprising a first semiconductor material of a first conductivity; (b) a second semiconductor layer of a second conductivity type opposite the first conductivity type on the outside of third pillar also embedded in the composite layers, the third pillar contacting both the first and second pillars; and (c) a storage layer provided between the second semiconductor layer and each of the conductor layer in the composite layers.
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