公开(公告)号：US08878284B2

公开(公告)日：2014-11-04

申请号：US13460523

申请日：2012-04-30

申请人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

发明人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

IPC分类号： H01L29/66

CPC分类号： H01L29/0692 ,  H01L29/87

摘要： A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

摘要翻译： 用于DMOS晶体管的保护电路包括阳极电路，其具有在第二导电类型（310,312）的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域（314）。 在第二导电类型（304）的第二重掺杂区域内具有第一导电类型（700）的多个第三重掺杂区域的阴极电路。 第一引线（202）连接到每个第三重掺杂区域（704），并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接（702）连接到第二重掺杂区域。 在阳极电路和阴极电路之间连接有SCR（400,402）。 DMOS晶体管具有连接到阳极电路的漏极（310,312,316）和连接到阴极电路的源极（304）。

公开(公告)号：US20130285137A1

公开(公告)日：2013-10-31

申请号：US13460523

申请日：2012-04-30

申请人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

发明人： Sameer Pendharkar ,  Suhail Murtaza ,  Juergen Wittmann

IPC分类号： H01L29/78

CPC分类号： H01L29/0692 ,  H01L29/87

摘要： A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

摘要翻译： 用于DMOS晶体管的保护电路包括阳极电路，其具有在第二导电类型（310,312）的第一轻掺杂区域内形成并电连接的第一导电类型的第一重掺杂区域（314）。 在第二导电类型（304）的第二重掺杂区域内具有第一导电类型（700）的多个第三重掺杂区域的阴极电路。 第一引线（202）连接到每个第三重掺杂区域（704），并且通过每两个第三重掺杂区域之间的至少三个间隔开的连接（702）连接到第二重掺杂区域。 在阳极电路和阴极电路之间连接有SCR（400,402）。 DMOS晶体管具有连接到阳极电路的漏极（310,312,316）和连接到阴极电路的源极（304）。

公开(公告)号：US06232188B1

公开(公告)日：2001-05-15

申请号：US09124854

申请日：1998-07-29

申请人： Suhail Murtaza ,  Amitava Chatterjee

发明人： Suhail Murtaza ,  Amitava Chatterjee

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/28562 ,  H01L29/66545

摘要： A method for forming a MOSFET transistor using a disposable gate process which has no need for a chemical mechanical polishing step to expose the disposable gate after deposition of the field dielectric. The field dielectric is deposited non-conformally by HDP-CVD over a disposable gate structure so that the disposable gate remains partially exposed. After deposition, the partially exposed disposable gate may then be removed by selective isotropic etch. In the space left by the removal of the disposable gate, the gate dielectric may be formed and the gate electrode may be deposited. Eliminating the need for exposure of the disposable gate by CMP eliminates the problem of polish rate dependence on gate pattern density.

摘要翻译： 一种使用一次性栅极工艺形成MOSFET晶体管的方法，该方法不需要在沉积场电介质之后进行化学机械抛光步骤来露出一次性栅极。 场致电介质通过HDP-CVD在一次性栅极结构上非保形沉积，使得一次性栅极保持部分暴露。 沉积后，可以通过选择性各向同性蚀刻去除部分暴露的一次性栅极。 在通过去除一次性栅极留下的空间中，可以形成栅极电介质并且可以沉积栅电极。 通过CMP消除对一次性栅极的曝光的需要消除了抛光率对栅极图案密度的依赖性的问题。