公开(公告)号：US20240274661A1

公开(公告)日：2024-08-15

申请号：US18507606

申请日：2023-11-13

申请人： Samsung Electronics Co., Ltd.

发明人： Sungyoung YOON ,  Jonghwa SHIN ,  Minyeul LEE ,  Sungyeol KIM ,  Taekjin KIM ,  Meehyun LIM ,  Sungyong LIM

IPC分类号： H01L29/06

CPC分类号： H01L29/0657 ,  H01L29/0692

摘要： A dielectric structure may include: an insulating layer extending in a first direction; a plurality of conductor layers disposed on a first surface of the insulating layer and spaced apart from each other in the first direction; at least one semiconductor layer disposed on a second surface of the insulating layer, opposite to the first surface, and overlapping each of at least two conductor layers adjacent to each other among the plurality of conductor layers in a second direction intersecting the first direction; a first protective layer covering the plurality of conductor layers on the first surface of the insulating layer; and a second protective layer covering the at least one semiconductor layer on the second surface of the insulating layer.

公开(公告)号：US20240258389A1

公开(公告)日：2024-08-01

申请号：US18592594

申请日：2024-03-01

申请人： ROHM CO., LTD.

发明人： Manabu YANAGIHARA ,  Hirotaka OTAKE

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

CPC分类号： H01L29/41758 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/7787

摘要： A semiconductor device includes a first semiconductor and a second semiconductor layer arranged thereon to generate a 2DEG in the first semiconductor layer. A source electrode and a drain electrode are arranged on the second semiconductor layer. A third semiconductor layer including an acceptor impurity is arranged on the second semiconductor layer between the source electrode and the drain electrode. A gate electrode is arranged on the third semiconductor layer. The second semiconductor layer defines a boundary between an element region including an FET and an element separation region. A guard ring is arranged on the second semiconductor layer in a peripheral part of the element region. The guard ring includes a fourth semiconductor layer arranged on the second semiconductor layer and including an acceptor impurity and a first electrode arranged on the fourth semiconductor layer and electrically connected to the source electrode or the 2GEG.

公开(公告)号：US20240258373A1

公开(公告)日：2024-08-01

申请号：US18162854

申请日：2023-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Yuan Kung ,  Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Fei-Yun Chen ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Yu-Chang Jong

IPC分类号： H01L29/08 ,  H01L21/302 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/302 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/66689 ,  H01L29/7833

摘要： An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.

公开(公告)号：US12051688B2

公开(公告)日：2024-07-30

申请号：US18261796

申请日：2022-09-27

申请人： Nuvoton Technology Corporation Japan

发明人： Kazumi Tsutsumida ,  Katsuyoshi Jokyu ,  Keiichi Murayama

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/866

CPC分类号： H01L27/0255 ,  H01L29/0692 ,  H01L29/7808 ,  H01L29/866

摘要： A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.

公开(公告)号：US12040389B2

公开(公告)日：2024-07-16

申请号：US17658335

申请日：2022-04-07

申请人： Silanna Asia Pte Ltd

发明人： Vadim Kushner ,  Nima Beikae

IPC分类号： H01L29/74 ,  H01L21/8228 ,  H01L21/84 ,  H01L23/528 ,  H01L23/538 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L29/7436 ,  H01L21/8228 ,  H01L21/84 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0623 ,  H01L27/067 ,  H01L27/0817 ,  H01L27/1203 ,  H01L29/0692

摘要： A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

公开(公告)号：US20240213317A1

公开(公告)日：2024-06-27

申请号：US18596461

申请日：2024-03-05

申请人： Samsung Electronics Co., Ltd.

发明人： Shigenobu MAEDA ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC分类号： H01L29/06 ,  B82Y10/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/0692 ,  B82Y10/00 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/775

摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

公开(公告)号：US20240136397A1

公开(公告)日：2024-04-25

申请号：US18403076

申请日：2024-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhih-Bin Chen ,  Ming Chyi Liu

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/7825

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate, and a drain region disposed within the substrate and separated from the source region. A plurality of separate isolation structures are disposed within the substrate. The plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another. A gate electrode is disposed within the substrate. The gate electrode includes a base region disposed between the source region and the plurality of separate isolation structures and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of separate isolation structures.

公开(公告)号：US20240128371A1

公开(公告)日：2024-04-18

申请号：US18472312

申请日：2023-09-22

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

发明人： YUICHI MORI

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/66734

摘要： A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface, in which a first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in this order in a thickness direction of the semiconductor substrate. The third semiconductor region is exposed from the first main surface. Trench gates are extended from the first main surface to reach the first semiconductor region beyond the third semiconductor region and the second semiconductor region. The trench gates are spaced from each other in a first direction. A part of the semiconductor substrate located between the trench gates adjacent to each other in the first direction includes a trunk portion extending along a second direction orthogonal to the first direction and a branch portion protruding from the trunk portion.

公开(公告)号：US20240105856A1

公开(公告)日：2024-03-28

申请号：US18458614

申请日：2023-08-30

申请人： Samsung Electronics Co., Ltd.

发明人： Jaehyok KO ,  Changsig KANG ,  Junhyeok KIM

IPC分类号： H01L29/861 ,  H01L27/02 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L27/0296 ,  H01L29/0692 ,  H01L29/417

摘要： An electrostatic discharge (ESD) device may include a semiconductor substrate, a base well in the semiconductor substrate, a first region including a first impurity region having a first conductivity type within the base well, a second region apart from the first region in a horizontal direction in the base well and including a second impurity region having a second conductivity type a first silicide layer at least partially overlapping the first impurity region in a vertical direction on the first impurity region, and a second silicide layer on the second impurity region and apart from the first silicide layer in the horizontal direction. The second silicide layer may at least partially overlap the second impurity region in the vertical direction. The second conductivity type may be opposite the first conductivity type.

公开(公告)号：US11942543B2

公开(公告)日：2024-03-26

申请号：US17852802

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun-Lin Tsai

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/7816 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42368

摘要： A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.