公开(公告)号：US20240015897A1

公开(公告)日：2024-01-11

申请号：US18126605

申请日：2023-03-27

Applicant: Samsung Display Co., Ltd.

Inventor： HYO-CHUL LEE ,  YOUNYEE KANG ,  JI-WON KIM ,  SEUNGIN BAEK ,  IN SOO WANG

IPC: H05K5/00 ,  H05K1/18

CPC classification number: H05K5/0018 ,  H05K1/189 ,  H05K5/0086 ,  H05K2201/10128 ,  H05K2201/09327

Abstract: A circuit board includes a first body part, a second body part and a connection part. The first body part includes a first contact surface and has a multi-layered structure. The second body part includes a second contact surface, has a multi-layered structure, and includes a first signal line spaced apart from the second contact surface. The connection part includes a third contact surface between the first contact surface and the second contact surface, and connects the first body part and the second body part to each other.

公开(公告)号：US20170053617A1

公开(公告)日：2017-02-23

申请号：US15141027

申请日：2016-04-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HYUN-SEOK HONG ,  HYO-CHUL LEE

IPC: G09G5/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC classification number: G09G5/003 ,  G09G3/2096 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0281 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2330/06 ,  G09G2370/08 ,  H05K1/0228 ,  H05K1/0296 ,  H05K1/147 ,  H05K1/181 ,  H05K2201/058 ,  H05K2201/10128

Abstract: A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.

Abstract translation: 显示装置包括印刷电路板（PCB）。 电源管理集成电路（PMIC）安装在PCB上，并被配置为产生第一至第四栅极时钟信号和第一至第四反向栅极时钟信号。 第一栅极时钟信号的相位部分地与第二至第四栅极时钟信号的相位重叠。 第一至第四反相栅极时钟信号中的每一个具有与第一至第四栅极时钟信号中的相应一个相反的相位。 栅极驱动器基于第一至第四栅极时钟信号和第一至第四反向栅极时钟信号产生多个栅极信号，并将多个栅极信号施加到多条栅极线。 显示面板连接到多条栅极线。

公开(公告)号：US20220030700A1

公开(公告)日：2022-01-27

申请号：US17239652

申请日：2021-04-25

Applicant: Samsung Display Co., Ltd.

Inventor： HYO-CHUL LEE ,  JI-WON KIM ,  IN SOO WANG

IPC: H05K1/02 ,  H05K1/18

Abstract: A circuit board for a display device includes: a signal line to transmit signal, a first metallic layer overlapping the signal line, a first conductive layer spaced apart from the first metallic layer, a base layer insulating the signal line from the first metallic layer and from the first conductive layer, and a first capacitor including a first terminal electrically coupled to the first metallic layer and a second terminal electrically coupled to the first conductive layer.

公开(公告)号：US20230023898A1

公开(公告)日：2023-01-26

申请号：US17656913

申请日：2022-03-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HYO-CHUL LEE ,  MIN JOO LEE

IPC: G09G3/20

Abstract: A display device includes a display panel including a plurality of pixels, a controller configured to output image data and a gated clock signal, the image data including a plurality of pixel data for the plurality of pixels, and a data driver configured to receive the image data and the gated clock signal from the controller, and to sample the image data in response to the gated clock signal. The controller detects a repeated data pattern where same pixel data is repeated in the image data, generates a clock enable signal having an off level in a period in which the repeated data pattern is transferred, and gates an input clock signal in response to the clock enable signal to produce the gated clock signal.