公开(公告)号：US20170170799A1

公开(公告)日：2017-06-15

申请号：US14966635

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Wil Choon Song

IPC: H03H7/38 ,  H05K1/18 ,  G06F17/50 ,  H01P3/08 ,  G06F13/38 ,  H05K3/00 ,  H05K1/02

CPC classification number: H03H7/38 ,  G06F13/382 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01P3/026 ,  H01P3/08 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/0005 ,  H05K9/0039 ,  H05K2201/09218 ,  H05K2201/0929 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09681

Abstract: Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.

公开(公告)号：US20170118842A1

公开(公告)日：2017-04-27

申请号：US14918678

申请日：2015-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. CHAMBERLIN ,  Andreas HUBER ,  Harald HUELS ,  Thomas STRACH ,  Thomas-Michael WINKEL

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US09629246B2

公开(公告)日：2017-04-18

申请号：US14811325

申请日：2015-07-28

Applicant: Infineon Technologies AG

Inventor： Qianli Mu ,  Cristian Gozzi ,  Michael Simcoe ,  Guillaume Bigny

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  H01L23/14

CPC classification number: H05K1/181 ,  H01L23/142 ,  H01L23/64 ,  H01L2224/49175 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/182 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/10166 ,  H05K2203/049

Abstract: A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

公开(公告)号：US09220164B2

公开(公告)日：2015-12-22

申请号：US14489555

申请日：2014-09-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi Kitajima

IPC: H04M1/00 ,  H05K1/02 ,  H05K1/18 ,  H01P3/16 ,  H04M1/02

CPC classification number: H05K1/0216 ,  H01P3/16 ,  H04M1/026 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/09327

Abstract: A high frequency module includes a ground mounting electrode connected to a ground terminal of a component, a first ground in-plane conductor in a multilayer substrate on a portion under the component and connected to the ground mounting electrode with a first ground interlayer connecting conductor, a signal mounting electrode connected to a signal terminal of the component, and a signal in-plane conductor provided in the multilayer substrate on a portion under the first ground in-plane conductor and connected to the specific signal mounting electrode with a signal interlayer connecting conductor. The first ground in-plane conductor is between the component and the signal in-plane conductor, and the signal interlayer connecting conductor is on an outer side portion of the first ground in-plane conductor when seen from above.

Abstract translation: 高频模块包括连接到部件的接地端子的接地安装电极，在部件下方的多个基板中的第一接地面内导体，并且与第一接地层间连接导体连接到接地安装电极， 连接到部件的信号端子的信号安装电极，以及设置在第一接地面内导体下的部分上的多层基板中的信号面内导体，并且与信号层间连接导体连接到特定信号安装电极 。 第一接地面内导体位于组件和信号面内导体之间，并且当从上方观察时，信号层间连接导体位于第一接地面内导体的外侧部分。

公开(公告)号：US20150264801A1

公开(公告)日：2015-09-17

申请号：US14297825

申请日：2014-06-06

Applicant: Honeywell International Inc.

Inventor： Kenneth Lee Martin ,  Lucilo De La Torre ,  James Frederick Peterson ,  Jonathan Cole

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0237 ,  G06F17/5077 ,  H01L21/486 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/09972 ,  H01L2924/00

Abstract: Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.

Abstract translation: 本文所述的系统和方法提供了其中具有多个故障容纳区域的电路板。 电路板包括第一故障容纳区域，该第一故障容纳区域至少部分地由耦合到地面的第一和第二金属层限定。 第一故障容纳区域包括在第一和第二金属层之间的第一信号层，在第一和第二金属层之间的第三金属层，第三金属层连接到第一信号层以提供第一信号层的返回路径 以及在第一和第二金属层之间的第四金属层，第四金属层连接到第一信号层以向第一信号层提供电力。 电路板还包括在第一故障容纳区域下方的多个层中的第二故障容纳区域。

公开(公告)号：US08026450B2

公开(公告)日：2011-09-27

申请号：US11978808

申请日：2007-10-30

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H05K1/00

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises a center segment distributing power and low-speed signaling, and outer segments for high-speed signaling. The segments use dielectric materials with different dielectric constants, with the outer segments supporting higher-speed signal transmission.

Abstract translation: 电路板包括分配功率和低速信号的中心段，以及用于高速信令的外部段。 这些段使用具有不同介电常数的介电材料，外部段支持更高速度的信号传输。

公开(公告)号：US07602062B1

公开(公告)日：2009-10-13

申请号：US11201515

申请日：2005-08-10

Applicant: Wen-Chou Wang

Inventor： Wen-Chou Wang

IPC: H01L21/00

CPC classification number: H01L23/49822 ,  H01L23/145 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09327 ,  H01L2924/00012

Abstract: Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material. Non-fibrous dielectric material layers are positioned below the signal metal layers and fibrous dielectric material layers are positioned below the power/ground plane metal layers. The package substrate combines in a single package substrate the advantages of rigidity, strength and relatively low CTE of a fibrous material with the capacity of a non-fibrous material to achieve fine resolution signal metal lines.

Abstract translation: 多层有机聚集半导体封装衬底具有层叠有纤维有机电介质材料和非纤维有机电介质材料的堆积层。 非纤维介电材料层位于信号金属层的下方，并且纤维介电材料层位于电力/接地平面金属层下方。 封装衬底在单个封装衬底中结合了纤维材料的刚度，强度和相对低的CTE的优点，具有非纤维材料的能力以实现精细分辨率信号金属线。

公开(公告)号：US07448132B2

公开(公告)日：2008-11-11

申请号：US11537754

申请日：2006-10-02

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/10

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US07301780B2

公开(公告)日：2007-11-27

申请号：US11414548

申请日：2006-05-01

Applicant: Shadi A. AbuGhazaleh ,  Robert C. Baxter ,  Rehan Mahmood ,  Alan C. Miller ,  Michael R. O'Connor

Inventor： Shadi A. AbuGhazaleh ,  Robert C. Baxter ,  Rehan Mahmood ,  Alan C. Miller ,  Michael R. O'Connor

IPC: H05K7/00

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 6 e, 6 and/or higher (e.g. 6 e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract translation: 补偿高级功能接线板，其可以包括直接位于接线板上的可拆卸模块或固定电子部件，其分开地或组合地能够提供诸如设备检测和功率插入的高级特征。 接线板提供PD /用户端的绝缘位移连接器（IDC）与使用非屏蔽双绞线电缆的任何标准接口类型之间的通信，例如在开关端的RJ45连接器，性能水平至少为3,5 ，6 e，6和/或更高（例如6 e或7）和等效性能水平，通过补偿用于提供高级功能的有源电子元件。 补偿部分通过主动和通信电路元件的分离和隔离来实现。

公开(公告)号：US07301775B2

公开(公告)日：2007-11-27

申请号：US11515763

申请日：2006-09-06

Applicant: Hiroshi Isoda

Inventor： Hiroshi Isoda

IPC: H05K7/02 ,  H03K9/00

CPC classification number: H04B1/28 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09327

Abstract: A tuner section is provided on one surface of a multilayered substrate, and a demodulating section on another surface of the multilayered substrate. The multilayered substrate further includes: an analog GND layer connected to the tuner section; a digital GND layer connected to the demodulating section; a shield GND layer which is provided between the analog GND layer and the digital GND layer; and insulation layers each provided (i) between the analog GND layer and shield GND layer, or (ii) between the digital GND layer and shield GND layer so as to electrically disconnect the shield GND layer from the analog GND layer and the digital GND layer. This allows the tuner section and the demodulating section to be respectively arranged on different surfaces of the substrate, for the purpose of downsizing of the receiving device, and yet allows the tuner section from being influenced by a harmonic signal generated in the demodulating section.