公开(公告)号：US20210249451A1

公开(公告)日：2021-08-12

申请号：US17003524

申请日：2020-08-26

Applicant: Samsung Display Co., LTD.

Inventor： Jae Uoon KIM ,  Hong Sick PARK ,  Jong Hyun CHOUNG

IPC: H01L27/12 ,  H01L27/32

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

公开(公告)号：US20230268356A1

公开(公告)日：2023-08-24

申请号：US18155982

申请日：2023-01-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong-Hwan RYU ,  Woo Jin CHO ,  Jong-Hyun CHOUNG ,  Jae Uoon KIM ,  Sun-Jin SONG ,  Hyun Duck CHO

IPC: H01L27/12 ,  G03F7/038 ,  G03F7/00

CPC classification number: H01L27/1288 ,  G03F7/0035 ,  G03F7/0382 ,  H01L27/1262 ,  C23F1/00

Abstract: A method of manufacturing a display device in a chamber in which a material including yttrium is coated on an inner surface includes: forming a first layer pattern by dry etching on a substrate; depositing a second layer material on the first layer pattern; forming a photoresist pattern on the second layer material; completing a second layer pattern by using the photoresist pattern as an etch mask; and performing an additional acid etching process by using an etching solution including at least one of hydrochloric acid, sulfuric acid, or nitric acid before the forming of the photoresist pattern on the second layer material after the dry etching to form the first layer pattern.

公开(公告)号：US20230116992A1

公开(公告)日：2023-04-20

申请号：US18084274

申请日：2022-12-19

Applicant: Samsung Display Co., LTD.

Inventor： Jae Uoon KIM ,  Hong Sick PARK ,  Jong Hyun CHOUNG

IPC: H01L27/12 ,  H10K59/123 ,  H10K59/131

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

公开(公告)号：US20220157856A1

公开(公告)日：2022-05-19

申请号：US17462803

申请日：2021-08-31

Applicant: Samsung Display Co., LTD.

Inventor： Jong Hyun CHOUNG ,  Jae Uoon KIM ,  Hyun Ah SUNG

IPC: H01L27/12

Abstract: A display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer include a pad opening which exposes a portion of the data conductive layer in the pad area. The third data capping layer has a higher etch rate than the first and second data capping layers for a same etchant.

公开(公告)号：US20210091161A1

公开(公告)日：2021-03-25

申请号：US16872594

申请日：2020-05-12

Applicant: Samsung Display Co., Ltd.

Inventor： Gyung Min BAEK ,  Ju Hyun LEE ,  Jae Uoon KIM ,  Hong Sick PARK ,  Hyun Eok SHIN

IPC: H01L27/32 ,  H01L51/52

Abstract: A device includes a substrate including a display area and a pad area; a first conductive layer on the substrate; and a first insulating film on the first conductive layer, the first insulating film having a first contact hole in the display area to expose the first conductive layer and a pad opening exposing the first conductive layer in the pad area, the first conductive layer being arranged such that in a first region covered by the first insulating film, a second conductive capping layer of the first conductive layer is entirely on a first conductive capping layer of the first conductive layer; in a second region overlapping the contact hole, the second conductive capping layer is entirely on the first conductive capping layer; and in a third region exposed by the pad opening, the second conductive capping layer exposes at least a portion of the first conductive capping layer.

公开(公告)号：US20200243563A1

公开(公告)日：2020-07-30

申请号：US16424388

申请日：2019-05-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hyun Choung ,  Jae Uoon KIM

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423

Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.