公开(公告)号：US09779703B2

公开(公告)日：2017-10-03

申请号：US14798193

申请日：2015-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： Hyun seok Hong ,  Jangseop Kim ,  Jinhyun Ko ,  HyunSeok Ko ,  Ung Choi

IPC: G09G5/395 ,  G09G5/18 ,  G09G5/00 ,  G09G3/20 ,  G09G3/36

CPC classification number: G09G5/395 ,  G09G3/2096 ,  G09G3/3648 ,  G09G5/003 ,  G09G5/006 ,  G09G5/18 ,  G09G2310/08 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2330/06 ,  G09G2360/18

Abstract: Provided is a timing controller configured to operate a display device. The timing controller includes a receiving unit receiving a still image signal; a transmitting unit outputting an output data used to display images; a clock frequency spreader generating a spread clock signal having a frequency value adjusted between first and second frequency values by modulating a reference clock signal; a memory system storing a first image data which corresponds to a first frame of an image, and outputting the first image data in response to the spread clock signal; and a still image managing unit communicating with the memory system in order to output the first image data as the output data. According to the timing controller, electro-magnetic interference may be reduced and operation errors of the display device may be prevented.

公开(公告)号：US09830848B2

公开(公告)日：2017-11-28

申请号：US14297192

申请日：2014-06-05

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Won Jeong ,  Hyun Seok Hong ,  Young-Su Kim ,  Jinhyun Ko ,  Hyelim Kim ,  Kyung-Uk Choi ,  Sangyoung Lee

IPC: G09G5/00 ,  G09G3/20 ,  H03K17/04 ,  G09G3/00

CPC classification number: G09G3/2092 ,  G09G3/006 ,  G09G2320/041 ,  H03K17/04

Abstract: An exemplary embodiment of the present invention discloses a voltage generation circuit of a display apparatus, including at least one resistor, a memory configured to store a resistance value set signal, a controller changing a resistance value of the resistor referring to the resistance value set stored in the memory, and a voltage generator connected to one end of the resistor and is configured to receive an input current corresponding to the resistance value of the resistor and generate a gate-on voltage corresponding to the input current.