公开(公告)号：US11955959B2

公开(公告)日：2024-04-09

申请号：US17613697

申请日：2019-05-29

Applicant: Mitsubishi Electric Corporation

Inventor： Yasushi Nakayama ,  Yoshiko Tamada ,  Takayoshi Miki ,  Shota Morisaki ,  Yukio Nakashima ,  Kenta Uchida ,  Keisuke Kimura ,  Tomonobu Mihara

IPC: H03K17/14 ,  H03K17/04 ,  H03K17/0412 ,  H03K17/28 ,  H02M1/088

CPC classification number: H03K17/14 ,  H03K17/04 ,  H03K17/0412 ,  H03K17/28 ,  H02M1/088

Abstract: A parallel driving device that drives parallel-connected semiconductor elements includes a control unit and a gate driving circuit. The control unit detects a temperature difference between the semiconductor elements on the basis of detected values by temperature sensors that detect temperatures of the individual semiconductor elements. The control unit generates a control signal for changing the timing at which to turn on a first semiconductor element specified from the semiconductor elements on the basis of the temperature difference. The gate driving circuit generates a first driving signal for driving the semiconductor elements, and generates a second driving signal that is the first driving signal delayed on the basis of the control signal, and applies the second driving signal to the first semiconductor element.

公开(公告)号：US20230412153A1

公开(公告)日：2023-12-21

申请号：US18461119

申请日：2023-09-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Takashi ICHIRYU ,  Hidetoshi ISHIDA

IPC: H03K3/012 ,  H03K17/04

CPC classification number: H03K3/012 ,  H03K17/04

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

公开(公告)号：US11695407B2

公开(公告)日：2023-07-04

申请号：US17543720

申请日：2021-12-06

Applicant: pSemi Corporation

Inventor： Alexander Dribinsky ,  Tae Youn Kim ,  Dylan J. Kelly ,  Christopher N. Brindle

IPC: H03K17/16 ,  H03K17/10 ,  H03K17/284 ,  H03K17/687 ,  H03K17/689 ,  H03K17/04 ,  H03K17/06 ,  H03K17/08

CPC classification number: H03K17/161 ,  H03K17/102 ,  H03K17/284 ,  H03K17/689 ,  H03K17/6874 ,  H03K17/04 ,  H03K17/06 ,  H03K17/08 ,  H03K2217/0009

Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

公开(公告)号：US10061558B2

公开(公告)日：2018-08-28

申请号：US15446045

申请日：2017-03-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki Ohshima

IPC: G11C19/00 ,  G11C11/24 ,  H03K3/037 ,  G06F5/01 ,  H03K3/356 ,  G06F1/16 ,  H03K19/00 ,  H03K17/00 ,  H03K17/04

CPC classification number: G06F5/01 ,  G06F1/16 ,  G06F5/015 ,  G11C11/24 ,  G11C19/00 ,  H03K3/037 ,  H03K3/356 ,  H03K17/002 ,  H03K17/04 ,  H03K19/0002

Abstract: A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.

公开(公告)号：US20180131360A1

公开(公告)日：2018-05-10

申请号：US15464375

申请日：2017-03-21

Applicant: MEDIATEK Inc.

Inventor： Chien-Hua Wu

IPC: H03K17/04

CPC classification number: H03K17/04 ,  H03K19/0185

Abstract: A driver circuit is provided. The driver circuit includes a differential driver, a first feedback passive circuit and a second feedback passive circuit. The differential driver includes a first half circuit and a second half circuit. The first half circuit has a first input point and a first output point. The second half circuit has a second input point and a second output point. The first feedback passive circuit is coupled to the second input point and the first output point. The second feedback passive circuit is coupled to the first input point and the second output point.

公开(公告)号：US20170126215A1

公开(公告)日：2017-05-04

申请号：US15403951

申请日：2017-01-11

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Jonathan Christian Crandall ,  Kenneth Norman Warren ,  Philip H. Thompson

IPC: H03K3/356 ,  H01L23/66 ,  H03F3/189 ,  H03F3/24 ,  H03K17/687 ,  H02M3/07

CPC classification number: H03K3/356104 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15184 ,  H02M3/07 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/451 ,  H03K17/04 ,  H03K17/04123 ,  H03K17/6872 ,  H03K17/693 ,  H04B7/24 ,  H01L2924/00014

Abstract: Apparatus and methods for level shifting in a radio frequency system are provided. In certain configurations, a radio frequency system includes a level shifter operable to provide level shifting to an input signal. The level shifter is biased by a bias voltage and powered by a supply voltage and a charge pump voltage. The radio frequency system further includes a charge pump configured to provide the charge pump voltage and to receive a mode signal operable to enable the charge pump in a first state and to disable the charge pump in a second state. The radio frequency system further includes a level shifter control circuit configured to control the bias voltage to track the charge pump voltage when the mode signal is in the first state, and to control the bias voltage with the supply voltage when the mode signal is in the second state.

公开(公告)号：US09612795B2

公开(公告)日：2017-04-04

申请号：US14200433

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuaki Ohshima

IPC: G11C19/00 ,  H03K3/037 ,  G11C11/24 ,  G06F5/01 ,  H03K3/356 ,  H03K17/00 ,  H03K17/04

CPC classification number: G06F5/01 ,  G06F1/16 ,  G06F5/015 ,  G11C11/24 ,  G11C19/00 ,  H03K3/037 ,  H03K3/356 ,  H03K17/002 ,  H03K17/04 ,  H03K19/0002

Abstract: A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time.

公开(公告)号：US09608542B2

公开(公告)日：2017-03-28

申请号：US14185849

申请日：2014-02-20

Applicant: Infineon Technologies Americas Corp.

Inventor： Tony Bahramian

IPC: H02M1/08 ,  H02M7/537 ,  H02M3/158 ,  H03K17/04 ,  H03K17/06 ,  H03K17/687

CPC classification number: H02M7/537 ,  H02M1/08 ,  H02M3/1584 ,  H02M3/1588 ,  H03K17/04 ,  H03K17/06 ,  H03K2017/6875 ,  Y02B70/1466

Abstract: According to an exemplary embodiment, a III-nitride power conversion circuit includes a gate driver having a plurality of cascaded inverters, each of the plurality of cascaded inverters including at least one III-nitride transistor. At least one of the plurality of cascaded inverters has a cutoff switch and a III-nitride depletion mode load where the cutoff switch is configured to disconnect the III-nitride depletion mode load so as to prevent current from flowing from a supply voltage of the at least one of the plurality of cascaded inverters. The cutoff switch of the at least one of the plurality of cascaded inverters can be driven by one of the plurality of cascaded inverters. The III-nitride power conversion circuit can also include an output driver driven by the gate driver where the output driver has a segmented III-nitride transistor. Furthermore, a selector circuit can be configured to selectively disable at least one segment of the segmented III-nitride transistor.

公开(公告)号：US09577626B2

公开(公告)日：2017-02-21

申请号：US14745818

申请日：2015-06-22

Applicant: Skyworks Solutions, Inc.

Inventor： Jonathan Christian Crandall ,  Kenneth Norman Warren ,  Philip H. Thompson

IPC: H03K17/04 ,  H03K17/0412 ,  H03K17/693

CPC classification number: H03K3/356104 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/15184 ,  H02M3/07 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/451 ,  H03K17/04 ,  H03K17/04123 ,  H03K17/6872 ,  H03K17/693 ,  H04B7/24 ,  H01L2924/00014

Abstract: Apparatus and methods for controlling radio frequency (RF) switches are disclosed. Provided herein are apparatus and methods for controlling RF switches. In certain configurations, an RF system includes a charge pump for generating a charge pump voltage, an RF switch, a level shifter for turning on or off the RF switch, and a level shifter control circuit for controlling the level shifter. The charge pump receives a mode signal used to enable or disable the charge pump. Additionally, the level shifter receives power in part from the charge pump voltage, and controls the RF switch based on a switch enable signal. The level shifter control circuit receives the mode signal and biases the level shifter with a bias voltage that changes based on a state of the mode signal.

Abstract translation: 公开了用于控制射频（RF）开关的装置和方法。 本文提供了用于控制RF开关的装置和方法。 在某些配置中，RF系统包括用于产生电荷泵电压的电荷泵，RF开关，用于导通或关断RF开关的电平移位器，以及用于控制电平移位器的电平移位器控制电路。 电荷泵接收用于启用或禁用电荷泵的模式信号。 此外，电平转换器部分地从电荷泵电压接收功率，并且基于开关使能信号来控制RF开关。 电平移位器控制电路接收模式信号并且以基于模式信号的状态改变的偏置电压来偏置电平移位器。

公开(公告)号：US09548729B2

公开(公告)日：2017-01-17

申请号：US14866193

申请日：2015-09-25

Applicant: Cypress Semiconductor Corporation

Inventor： Toru Miyamae

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687

CPC classification number: H03K17/04 ,  H03K17/04123 ,  H03K17/16 ,  H03K17/164 ,  H03K17/687

Abstract: A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.

Abstract translation: 开关电路包括驱动电路DRV2，其串联设置在输入电压和地之间的多个晶体管开关中输出用于导通和关断位于相对于负载的低电位侧的第一晶体管开关M2的电压 ; 以及控制电路，其使得驱动电路DRV2输出第一电压，该第一电压在第一晶体管开关M2关断时驱动电路DRV2的输出电压上升，使第一晶体管开关M2导通，并使驱动电路DRV2暂停 在驱动电路DRV2输出第一电压之后驱动电路DRV2的输出电压下降时的第一电压的输出。