公开(公告)号：US20180144680A1

公开(公告)日：2018-05-24

申请号：US15819367

申请日：2017-11-21

Applicant: Samsung Display Co., Ltd.

Inventor： SHIMHO YI ,  SUNG-IN KANG ,  KYUNHO KIM ,  SEUNGHWAN MOON

IPC: G09G3/20 ,  G05F3/24

CPC classification number: G09G3/2092 ,  G05F3/24 ,  G09G3/006 ,  G09G3/2096 ,  G09G2300/0819 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/04 ,  G09G2330/12

Abstract: A power voltage generating circuit includes an input part, a clock determining part and a plurality of switches. The input part receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals. The clock determining part determines a normal mode and an abnormal mode based on a number of the plurality of peak signals. The switches blocks outputs of the plurality of clock signals in the abnormal mode.