公开(公告)号：US20230252944A1

公开(公告)日：2023-08-10

申请号：US18075759

申请日：2022-12-06

Applicant: Samsung Display Co., Ltd.

Inventor： KIHYUN PYUN ,  SUNG-IN KANG

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2330/028 ,  G09G2360/16 ,  G09G2330/021 ,  G09G2300/0842

Abstract: A display device includes a display panel including a plurality of pixels, a power supply which provides a driving voltage to the pixels, and a controller which outputs a first signal by comparing a sensing driving current generated by sensing driving currents flowing through the pixels with a limit current, outputs a second signal by comparing a load of previous frame data with a limit load, and outputs a driving voltage control signal for controlling the driving voltage to the power supply based on the first signal and the second signal.

公开(公告)号：US20180144680A1

公开(公告)日：2018-05-24

申请号：US15819367

申请日：2017-11-21

Applicant: Samsung Display Co., Ltd.

Inventor： SHIMHO YI ,  SUNG-IN KANG ,  KYUNHO KIM ,  SEUNGHWAN MOON

IPC: G09G3/20 ,  G05F3/24

CPC classification number: G09G3/2092 ,  G05F3/24 ,  G09G3/006 ,  G09G3/2096 ,  G09G2300/0819 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/04 ,  G09G2330/12

Abstract: A power voltage generating circuit includes an input part, a clock determining part and a plurality of switches. The input part receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals. The clock determining part determines a normal mode and an abnormal mode based on a number of the plurality of peak signals. The switches blocks outputs of the plurality of clock signals in the abnormal mode.