公开(公告)号：US12283252B2

公开(公告)日：2025-04-22

申请号：US18599524

申请日：2024-03-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Tae Seok Ha ,  Koung Soo Kim ,  Kyu Jin Park ,  Sung Jae Park ,  Seung Woon Shin ,  Woon Rok Jang

IPC: G09G3/3291

Abstract: A display device includes a display panel including a plurality of pixels, a data driver configured to provide data voltages to the pixels, and a gate driver configured to provide gate signals to the pixels. The display device also includes a controller configured to control the data driver and the gate driver, and to control the magnitude of a sensing initialization voltage applied to the pixels based on a frame rate value when operating in a variable frame mode.

公开(公告)号：US11942045B2

公开(公告)日：2024-03-26

申请号：US17493240

申请日：2021-10-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Tae Seok Ha ,  Koung Soo Kim ,  Kyu Jin Park ,  Sung Jae Park ,  Seung Woon Shin ,  Woon Rok Jang

IPC: G09G3/3291

CPC classification number: G09G3/3291 ,  G09G2300/0842 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2330/028

Abstract: A display device includes a display panel including a plurality of pixels, a data driver configured to provide data voltages to the pixels, and a gate driver configured to provide gate signals to the pixels. The display device also includes a controller configured to control the data driver and the gate driver, and to control the magnitude of a sensing initialization voltage applied to the pixels based on a frame rate value when operating in a variable frame mode.

公开(公告)号：US10917010B2

公开(公告)日：2021-02-09

申请号：US16437572

申请日：2019-06-11

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun Pyun ,  Seung Woon Shin ,  Jong Young Yun

IPC: H02M3/157 ,  H02M3/158 ,  H02M1/08 ,  H03K7/08 ,  H02M1/00 ,  H02M3/156

Abstract: A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.