DISPLAY PANEL
    1.
    发明公开
    DISPLAY PANEL 审中-公开

    公开(公告)号:US20230269984A1

    公开(公告)日:2023-08-24

    申请号:US18111998

    申请日:2023-02-21

    CPC classification number: H10K59/1315

    Abstract: A display panel includes a base layer, a first conductive layer disposed on the base layer and including a power pattern, a second conductive layer disposed on the first conductive layer, and a first insulating layer disposed between the first conductive layer and the second conductive layer. The first insulating layer is provided with at least one first contact hole defined therethrough and disposed at an upper side in a plan view and at least one second contact hole defined therethrough and disposed at a lower side in a plan view, the first conductive layer is electrically connected to the second conductive layer via the at least one first contact hole and the at least one second contact hole, and a number of the at least one first contact hole is equal to a number of the at least one second contact hole.

    DISPLAY DEVICE
    2.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20240265872A1

    公开(公告)日:2024-08-08

    申请号:US18507102

    申请日:2023-11-13

    Abstract: A display device includes a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer and a third conductive layer disposed on the second conductive layer. The first conductive layer includes a data line extending in a first direction. The second conductive layer includes a first scan line extending in a second direction intersecting the first direction, and a second scan line spaced apart from the first scan line and extending in the second direction. The third conductive layer includes a first driving voltage line extending in the second direction, a first common voltage line spaced apart from the first driving voltage line and extending in the second direction, and a pixel electrode disposed between the first driving voltage line and the first common voltage line in a plan view.

    GATE DRIVER AND DISPLAY DEVICE HAVING THE SAME

    公开(公告)号:US20230402012A1

    公开(公告)日:2023-12-14

    申请号:US18077405

    申请日:2022-12-08

    Abstract: A gate driver includes stages. Each stage includes: a first output part for outputting a carry signal in response to a voltage of a first node; a first input part for controlling the voltage of the first node in response to a previous carry signal; a second input part for controlling the voltage of the first node in response to a first next carry signal; a second output part for outputting a scan signal in response to the voltage of the first node; a third output part for outputting a sensing signal in response to the voltage of the first node; and a scan signal control part for applying a first low power voltage to an output terminal of the second output part to which the scan signal is output in response to a second next carry signal of which a pulse is generated before the first next carry signal.

    DISPLAY PANEL
    5.
    发明公开
    DISPLAY PANEL 审中-公开

    公开(公告)号:US20230247878A1

    公开(公告)日:2023-08-03

    申请号:US18100788

    申请日:2023-01-24

    CPC classification number: H10K59/1315 H10K59/1213 H10K59/8792

    Abstract: A display panel includes a base layer, first to third pixels, data lines, a first voltage line that is connected to the first to third pixels and that extends in a second direction, and an initialization voltage line that is connected to the first to third pixels and that extends in the second direction. Each of the first to third pixels includes a light-emitting element including an anode, a first transistor that is connected between the first voltage line and the anode and that includes a gate electrode, a second transistor connected with a data line of the data lines, a third transistor that is connected between the initialization voltage line and a node and that includes a gate electrode, and a fourth transistor that is connected between the node and the anode and that includes a gate electrode connected with the first voltage line.

    DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

    公开(公告)号:US20230178031A1

    公开(公告)日:2023-06-08

    申请号:US17864764

    申请日:2022-07-14

    CPC classification number: G09G3/3291 G09G2330/028 G09G2310/0272

    Abstract: A display device includes a display panel including a plurality of pixels, a gate driver which provides a gate signal to corresponding pixels of the plurality of pixels, a data driver which provides a data voltage to the corresponding pixels of the plurality of pixels, a power voltage generator which provides a pixel power voltage to each of the plurality of pixels, and provides a gate power voltage to the gate driver, and a controller which provides a gate control signal to the gate driver. The pixel power voltage, the data voltage, and the gate control signal sequentially have a ground voltage level in response to a power-off signal.

    GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

    公开(公告)号:US20240395191A1

    公开(公告)日:2024-11-28

    申请号:US18437029

    申请日:2024-02-08

    Abstract: A gate driving circuit includes a stage which outputs a scan signal based on a scan clock signal, a voltage of a first node, and a voltage of a second node, and outputs a sensing signal based on a sensing clock signal, a voltage of the first node, and a voltage of the second node. The stage includes a second sensing portion including transistors electrically connected in series and a first pull-up control portion including transistors electrically connected in series, the transistors including control electrodes electrically connected to each other. A first intermediate node between the transistors of the second sensing portion is separated from a second intermediate node between the transistors of the first pull-up control portion.

    DISPLAY DEVICE
    8.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20240161701A1

    公开(公告)日:2024-05-16

    申请号:US18212512

    申请日:2023-06-21

    Abstract: A display device includes a display panel and a gate driver. The gate driver includes an N-th stage (where N is a natural number) configured to output an N-th scan gate signal and output an N-th sensing gate signal. The N-th stage includes a compensator, a sixth transistor including a control electrode connected to a first node, and a ninth transistor including a control electrode connected to the first node. In a variable frequency mode, the compensator outputs a second signal to the first node in response to a first signal, and the sixth transistor does not output the N-th scan gate signal when the ninth transistor outputs the N-th sensing gate signal based on the sensing clock signal, the voltage of the first node, and the voltage of the second node.

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