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公开(公告)号:US20230276619A1
公开(公告)日:2023-08-31
申请号:US18049061
申请日:2022-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungmin Ju , Gyuhyun Kil , Hyebin Choi , Doosan Back , Ahrang Choi , Jung-Hoon Han
IPC: H01L27/108
CPC classification number: H01L27/10897 , H01L27/10814 , H01L27/10894
Abstract: A semiconductor device includes a substrate having first and second active patterns therein, which are spaced apart from each other. The first active pattern has a top surface that is elevated relative to a top surface of the second active pattern. A channel semiconductor layer is provided on the top surface of the first active pattern. A first gate pattern is provided, which includes a first insulating pattern, on the channel semiconductor layer. A second gate pattern is provided, which includes a second insulating pattern having a thickness greater than a thickness of the first insulating pattern, on the top surface of the second active pattern.
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公开(公告)号:US20230209808A1
公开(公告)日:2023-06-29
申请号:US17880723
申请日:2022-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ahrang Choi , Chansic Yoon , Hoin Ryu , Junghoon Han
IPC: H01L27/108
CPC classification number: H01L27/10823 , H01L27/10814
Abstract: A semiconductor device includes active regions defined by a device isolation region in a substrate; trenches extending in a first direction to intersect the active regions; buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions; a buffer structure covering the active regions, the isolation region, and the buried gate structures; bit line structures extending in a second direction intersecting the first direction on the active regions and connected to the active regions; storage node contacts between the bit line structures, penetrating through the buffer structure and in contact with the active regions; and capacitor structures in contact with an upper surface of the storage node contacts.
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