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公开(公告)号：US12040231B2
公开(公告)日：2024-07-16
申请号：US17201457
申请日：2021-03-15
发明人： Junghoon Han , Juik Lee
IPC分类号： H01L21/768 , H01L23/31 , H01L23/48 , H01L23/528
CPC分类号： H01L21/76898 , H01L21/7682 , H01L21/76831 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/528
摘要： A semiconductor device includes a substrate, an interlayer insulating layer covering an upper surface of the substrate, an individual device in the interlayer insulating layer, a lower insulating layer covering a lower surface of the substrate, a through-silicon-via (TSV) structure extending through the substrate, the interlayer insulating layer and the lower insulating layer, a conductive pad connected to an upper end of the TSV structure, a via insulating layer surrounding the TSV structure, a capping insulating layer surrounding the TSV structure outside the via insulating layer. The via insulating layer and the capping insulating layer have an air gap therebetween. A portion of the air gap extends into the lower insulating layer.
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公开(公告)号：US20230230915A1
公开(公告)日：2023-07-20
申请号：US18127342
申请日：2023-03-28
发明人： Yeonjin Lee , Junyong Noh , Minjung Choi , Junghoon Han , Yunrae Cho
IPC分类号： H01L23/522 , H01L23/31 , H01L23/00 , H01L23/528 , H01L23/48 , H01L23/532 , H01L21/768 , H01L23/485 , H01L21/82 , H01L21/56 , H01L21/78
CPC分类号： H01L23/5222 , H01L23/3185 , H01L24/05 , H01L23/5283 , H01L23/481 , H01L23/53295 , H01L21/76832 , H01L23/485 , H01L23/5226 , H01L21/82 , H01L21/561 , H01L21/78 , H01L23/562 , H01L2224/0237 , H01L2224/024
摘要： A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
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3.发明授权公开(公告)号：US11342235B2
公开(公告)日：2022-05-24
申请号：US16898943
申请日：2020-06-11
发明人： Minjung Choi , Junyong Noh , Yeonjin Lee , Junghoon Han
摘要： A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
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公开(公告)号：US12080663B2
公开(公告)日：2024-09-03
申请号：US18377530
申请日：2023-10-06
发明人： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
CPC分类号： H01L24/05 , H01L21/561 , H01L24/13 , H01L24/73 , H01L24/96 , H01L2224/0401 , H01L2224/12105 , H01L2224/13099 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US11776894B2
公开(公告)日：2023-10-03
申请号：US16848246
申请日：2020-04-14
发明人： Yeonjin Lee , Junyong Noh , Minjung Choi , Junghoon Han , Yunrae Cho
IPC分类号： H01L23/48 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/00 , H01L23/31 , H01L21/768 , H01L25/065 , H01L21/76 , H01L23/525 , H01L21/78 , H01L21/82 , H01L23/528 , H01L21/56
CPC分类号： H01L23/5222 , H01L21/561 , H01L21/76832 , H01L21/78 , H01L21/82 , H01L23/3185 , H01L23/481 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53295 , H01L24/05 , H01L23/562 , H01L2224/024 , H01L2224/0237
摘要： A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
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公开(公告)号：US20220278061A1
公开(公告)日：2022-09-01
申请号：US17747190
申请日：2022-05-18
发明人： Eunyoung Jeong , Juik Lee , Junghoon Han
IPC分类号： H01L23/00
摘要： Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.
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公开(公告)号：US09761591B2
公开(公告)日：2017-09-12
申请号：US15148405
申请日：2016-05-06
发明人： Eunjung Kim , Sohyun Park , Bong-Soo Kim , Yoosang Hwang , Dong-Wan Kim , Junghoon Han
IPC分类号： H01L21/20 , H01L27/108 , H01L21/56 , H01L21/311 , H01L49/02 , H01L21/3105 , H01L21/027
CPC分类号： H01L27/10894 , H01L21/0274 , H01L21/31051 , H01L21/31144 , H01L21/565 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10897 , H01L27/11582 , H01L28/00 , H01L28/60
摘要： A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.
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公开(公告)号：US20230209808A1
公开(公告)日：2023-06-29
申请号：US17880723
申请日：2022-08-04
发明人： Ahrang Choi , Chansic Yoon , Hoin Ryu , Junghoon Han
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L27/10814
摘要： A semiconductor device includes active regions defined by a device isolation region in a substrate; trenches extending in a first direction to intersect the active regions; buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions; a buffer structure covering the active regions, the isolation region, and the buried gate structures; bit line structures extending in a second direction intersecting the first direction on the active regions and connected to the active regions; storage node contacts between the bit line structures, penetrating through the buffer structure and in contact with the active regions; and capacitor structures in contact with an upper surface of the storage node contacts.
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公开(公告)号：US11362053B2
公开(公告)日：2022-06-14
申请号：US16922828
申请日：2020-07-07
发明人： Eunyoung Jeong , Juik Lee , Junghoon Han
IPC分类号： H01L23/00
摘要： Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.
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公开(公告)号：US11049827B2
公开(公告)日：2021-06-29
申请号：US16795658
申请日：2020-02-20
发明人： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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