公开(公告)号：US20210357287A1

公开(公告)日：2021-11-18

申请号：US17132028

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoun KIM ,  Kijun LEE ,  Chanki KIM ,  Myungkyu LEE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15

Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.

公开(公告)号：US20210083687A1

公开(公告)日：2021-03-18

申请号：US16809949

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun LEE ,  Chanki KIM ,  Sunghye CHO ,  Myungkyu LEE

IPC: H03M13/11 ,  H03M13/15 ,  G06F17/16

Abstract: A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.