公开(公告)号：US20240249793A1

公开(公告)日：2024-07-25

申请号：US18394627

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin YOU ,  Eunae LEE ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Kyomin SOHN

IPC: G11C29/52 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C29/52 ,  G11C11/40615 ,  G11C11/4085

Abstract: A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

公开(公告)号：US20160103735A1

公开(公告)日：2016-04-14

申请号：US14877448

申请日：2015-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun LEE ,  Myungkyu Lee ,  Sejin Lim ,  Junjin Kong

IPC: G06F11/10 ,  H03M13/15

CPC classification number: H03M13/3715 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/157

Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.

Abstract translation: 本发明构思涉及纠错解码器校正从非易失性存储器读取的数据的错误的操作方法。 操作方法可以包括从非易失性存储器接收数据，以简化模式对接收到的数据执行第一纠错，并且当在简化模式中第一错误校正失败时执行相对于 接收到的数据处于完整模式。 当执行简化模式的第一纠错时，可以省略完整模式的第二纠错的一部分操作。

公开(公告)号：US20230141789A1

公开(公告)日：2023-05-11

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Eunae LEE ,  Byeonggyu PARK ,  Yeonggeol SONG

IPC: G11C11/406 ,  G11C11/4093

CPC classification number: G11C11/40615 ,  G11C11/4093 ,  G11C11/40618

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US20210191809A1

公开(公告)日：2021-06-24

申请号：US16909730

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggeol SONG ,  Sungrae KIM ,  Kijun LEE

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/4093 ,  H01L25/065

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

公开(公告)号：US20140056064A1

公开(公告)日：2014-02-27

申请号：US14068143

申请日：2013-10-31

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Jaehong KIM ,  Kijun LEE ,  Yong June KIM ,  Heeseok EUN

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/26

Abstract: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

Abstract translation: 提供了一种存储器系统及其操作方法。 操作方法用不同的读取电压至少一次读取观察存储器单元以配置第一读取数据符号，至少用不同的读取电压读取与观察存储器单元相邻的多个干扰存储器单元以配置第二读取数据 符号，并且基于第一读取数据符号和第二读取数据符号确定观察存储器单元的逻辑值。

公开(公告)号：US20240201868A1

公开(公告)日：2024-06-20

申请号：US18588599

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20210083687A1

公开(公告)日：2021-03-18

申请号：US16809949

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun LEE ,  Chanki KIM ,  Sunghye CHO ,  Myungkyu LEE

IPC: H03M13/11 ,  H03M13/15 ,  G06F17/16

Abstract: A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.

公开(公告)号：US20140108748A1

公开(公告)日：2014-04-17

申请号：US14054964

申请日：2013-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kijun LEE ,  Junjin KONG ,  Dong-Min SHIN ,  Kyeongcheol YANG ,  Seung-Chan LIM

IPC: G06F12/00

CPC classification number: G06F12/00 ,  H03M13/1111 ,  H03M13/1191 ,  H03M13/13 ,  H03M13/6362 ,  H04L1/0009

Abstract: An operating method of a controller includes selecting bits of code word to be punctured; detecting locations of incapable bits of an input word based on locations of the bits to be punctured and a structure of a generation matrix calculation unit; refreezing the input word such that frozen bits and incapable bits of the input word overlap; generating input word bits by replacing information word bits with frozen bits based on the refreezing result; generating the code word by performing generation matrix calculation on the input word bits; generating output bits by puncturing the code word based on locations of the bits to be punctured; and transmitting the output bits to a nonvolatile memory device.

Abstract translation: 控制器的操作方法包括选择要被穿孔的代码字的位; 基于要被删截的位的位置检测输入字的不能位的位置和生成矩阵计算单元的结构; 重新冻结输入字，使得输入字的冻结位和无效位重叠; 通过基于重新冻结结果将具有冻结位的信息字位替换来产生输入字位; 通过对输入字位执行生成矩阵计算来生成码字; 通过基于要被穿孔的比特的位置来对码字进行删截来产生输出比特; 并将输出比特发送到非易失性存储器件。

公开(公告)号：US20230163786A1

公开(公告)日：2023-05-25

申请号：US17988140

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Sunghye CHO ,  Jin-Hoon JANG ,  Isak HWANG

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/09

CPC classification number: H03M13/1174 ,  H03M13/1575 ,  H03M13/098

Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

公开(公告)号：US20230146904A1

公开(公告)日：2023-05-11

申请号：US17984430

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu LEE ,  Kijun LEE ,  Sunghye CHO ,  Sungrae KIM

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/159 ,  H03M13/611

Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.