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    Semiconductor memory package including stacked layers and memory device and semiconductor memory system having the same
    1.
    发明授权
    Semiconductor memory package including stacked layers and memory device and semiconductor memory system having the same 有权

    公开(公告)号：US10096577B2

    公开(公告)日：2018-10-09

    申请号：US15622154

    申请日：2017-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Kim ,  Chi-sung Oh

    IPC: H01L25/065 ,  H01L23/00 ,  H05K1/11

    Abstract: A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.

    SEMICONDUCTOR MEMORY PACKAGE INCLUDING STACKED LAYERS AND MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM HAVING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY PACKAGE INCLUDING STACKED LAYERS AND MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM HAVING THE SAME 审中-公开

    公开(公告)号：US20180012867A1

    公开(公告)日：2018-01-11

    申请号：US15622154

    申请日：2017-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Kim ,  Chi-sung Oh

    IPC: H01L25/065 ,  H05K1/11 ,  H01L23/00

    CPC classification number: H01L25/0657 ,  H01L24/14 ,  H05K1/115

    Abstract: A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.

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