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1.发明申请公开(公告)号：US20180012867A1
公开(公告)日：2018-01-11
申请号：US15622154
申请日：2017-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Kim , Chi-sung Oh
IPC: H01L25/065 , H05K1/11 , H01L23/00
CPC classification number: H01L25/0657 , H01L24/14 , H05K1/115
Abstract: A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.
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2.发明授权公开(公告)号：US09385730B2
公开(公告)日：2016-07-05
申请号：US14272975
申请日：2014-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan Bae , Kee-won Kwon , Kyoungho Kim , Jung Hoon Chun , Youngsoo Sohn , Seok Kim
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。
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公开(公告)号：US09654118B2
公开(公告)日：2017-05-16
申请号：US15179202
申请日：2016-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan Bae , Kee-Won Kwon , Kyungho Kim , Jung Hoon Chun , Youngsoo Sohn , Seok Kim
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
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公开(公告)号：US10096577B2
公开(公告)日：2018-10-09
申请号：US15622154
申请日：2017-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seok Kim , Chi-sung Oh
IPC: H01L25/065 , H01L23/00 , H05K1/11
Abstract: A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.
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