公开(公告)号：US20220399359A1

公开(公告)日：2022-12-15

申请号：US17693875

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub KIM ,  Dongmin KYEON ,  Shinyoung KIM ,  Hayan PARK ,  Youngsun CHO ,  Changhyun HUR

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a memory cell region positioned on a substrate and comprising a real memory cell region and a dummy memory cell region; and a connection region extending in a first direction parallel to a surface of the substrate in the memory cell region. The dummy memory cell region includes a plurality of dummy vertical channel structures spaced apart from each other. Each of the plurality of dummy vertical channel structures includes a vertical channel pattern in contact with the substrate while penetrating a stack structure comprising a plurality of insulating layers and a plurality of gate electrodes repeatedly stacked in a third direction perpendicular to a surface of the substrate. A protection pattern is disposed to surround the vertical channel pattern of at least one of the plurality of dummy vertical channel structures.

公开(公告)号：US20240324219A1

公开(公告)日：2024-09-26

申请号：US18604844

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choasub KIM ,  Chungjin KIM ,  Youngho KWON ,  Jungho LEE

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: An integrated circuit device comprising: a substrate; a stack structure comprising interlayer insulating layers and gate electrodes; and a channel structure in the stack structure, wherein the gate electrodes comprise a first upper gate electrode at a highest position and a second upper gate electrode at a second-highest position, the interlayer insulating layers comprises a first interlayer insulating layer between the first upper gate electrode and the second upper gate electrode with a first thickness, a second interlayer insulating layer that has a second thickness, a lower surface of the first upper gate electrode is at a farther distance than or at an equal distance to a lower surface of the pad structure from the substrate, and an upper surface of the second upper gate electrode is at a closer distance than or at an equal distance to the lower surface of the pad structure from the substrate.

公开(公告)号：US20220293622A1

公开(公告)日：2022-09-15

申请号：US17668824

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub KIM ,  Bongtae PARK ,  Jae-Joo SHIM ,  Sungil CHO

IPC: H01L27/11565 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device may include a first cell block including a first electrode structure including first electrodes stacked on a substrate, and first channels penetrating the first electrode structure, and a second cell block including a second electrode structure including second electrodes stacked on the substrate, and second channels penetrating the second electrode structure. The first and second electrode structures may extend in a first direction. The first electrode structure may have a first width in a second direction, and the second electrode structure may have a second width greater than the first width. A side surface of the first electrode structure and the first channel adjacent thereto may be apart from each other by a first distance, and a side surface of the second electrode structure and the second channel adjacent thereto may be apart from each other by a second distance different from the first distance.