公开(公告)号：US20230005942A1

公开(公告)日：2023-01-05

申请号：US17678473

申请日：2022-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Jae-Joo SHIM ,  Dong-Sik LEE ,  Bongtae PARK

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

Abstract: A 3D semiconductor memory device includes a substrate, a stack structure comprising interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, vertical channel structures penetrating the stack structure, a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer, an insulating layer covering the substrate and the stack structure, contact plugs penetrating the insulating layer so as to be connected to the gate electrodes of the stack structure, and a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be connected to a peripheral circuit transistor. A bottom surface of the first conductive contact is at a level lower than a bottom surface of the spacer.

公开(公告)号：US20220149056A1

公开(公告)日：2022-05-12

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L27/108 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20240315021A1

公开(公告)日：2024-09-19

申请号：US18183469

申请日：2023-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siwan KIM ,  Juwon IM ,  Jonghyun PARK ,  Sori LEE ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate and circuit devices; and a second semiconductor structure including a second substrate on the first semiconductor structure and having a first region and a second region, gate electrodes in the first region and stacked in a first direction, and extending in the second region by different lengths in a second direction, channel structures extending by penetrating through the gate electrodes, separation regions penetrating through the gate electrodes, extending in the second direction, spaced apart from each other in a third direction, and defining a center block region and an edge block region, and substrate insulating layers in the second substrate between the separation regions in the second region. A width of the substrate insulating layers in the third direction is greater in the edge block region than in the center block region.

公开(公告)号：US20240090211A1

公开(公告)日：2024-03-14

申请号：US18135349

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon KIM ,  Sung-Min HWANG ,  Dong-Sik LEE ,  Seunghyun CHO ,  Bongtae PARK ,  Jae-Joo SHIM

IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.

公开(公告)号：US20230094302A1

公开(公告)日：2023-03-30

申请号：US17747412

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Dongsung WOO ,  Tae Gon LEE ,  Bongtae PARK ,  Jae-Joo SHIM ,  Tae-Chul JUNG

IPC: H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.

公开(公告)号：US20230026774A1

公开(公告)日：2023-01-26

申请号：US17709803

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Taewon KANG ,  Dongsung WOO ,  Taegon LEE ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/108

Abstract: A semiconductor device and a data storage system including the same, the semiconductor device including a substrate structure; a stack structure; a vertical memory structure; a vertical dummy structure; and an upper separation pattern, wherein hen viewed on a plane at a first height level, higher than a height level of a lowermost end of the upper separation pattern, the dummy channel layer includes a first dummy channel region facing the dummy data storage layer and a second dummy channel region facing the dummy data storage layer, the first dummy channel region having a thickness different from a thickness of the second dummy channel region.

公开(公告)号：US20220293622A1

公开(公告)日：2022-09-15

申请号：US17668824

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub KIM ,  Bongtae PARK ,  Jae-Joo SHIM ,  Sungil CHO

IPC: H01L27/11565 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device may include a first cell block including a first electrode structure including first electrodes stacked on a substrate, and first channels penetrating the first electrode structure, and a second cell block including a second electrode structure including second electrodes stacked on the substrate, and second channels penetrating the second electrode structure. The first and second electrode structures may extend in a first direction. The first electrode structure may have a first width in a second direction, and the second electrode structure may have a second width greater than the first width. A side surface of the first electrode structure and the first channel adjacent thereto may be apart from each other by a first distance, and a side surface of the second electrode structure and the second channel adjacent thereto may be apart from each other by a second distance different from the first distance.

公开(公告)号：US20210035991A1

公开(公告)日：2021-02-04

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye KIM ,  Jaehoon LEE ,  Jiyoung KIM ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/112 ,  H01L27/32 ,  H01L27/11585

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20170221755A1

公开(公告)日：2017-08-03

申请号：US15398090

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang SIM ,  Hojun SEONG ,  Bongtae PARK ,  Woo-Jung KIM

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/11529 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11573

Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.

公开(公告)号：US20160013196A1

公开(公告)日：2016-01-14

申请号：US14858756

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Hyun YOU ,  Hyeong PARK ,  Bongtae PARK ,  Jeehoon HAN

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L29/788 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。