公开(公告)号：US20220253692A1

公开(公告)日：2022-08-11

申请号：US17400353

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongseok YU ,  Yoojin KIM ,  Seongwook PARK ,  Hyun Sun PARK ,  Sehwan LEE ,  Jun-Woo JANG ,  Deokjin JOO

IPC: G06N3/08 ,  G06F9/30 ,  G06F7/02

Abstract: Disclosed is a method and apparatus of operating a neural network. The neural network operation method includes receiving data for the neural network operation, verifying whether competition occurs between a first data traversal path corresponding to a first operation device and a second data traversal path corresponding to a second operation device, determining first operand data and second operand data from among the data using a result of the verifying and a priority between the first data traversal path and the second data traversal path, and performing the neural network operation based on the first operand data and the second operand data.

公开(公告)号：US20200159495A1

公开(公告)日：2020-05-21

申请号：US16683626

申请日：2019-11-14

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Deokjin JOO ,  Hossein MORADIAN SARDROUDI ,  Sujeong JO ,  Kiyoung CHOI

IPC: G06F7/505 ,  G06N3/063 ,  G06N3/04

Abstract: A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.

公开(公告)号：US20230169340A1

公开(公告)日：2023-06-01

申请号：US18089696

申请日：2022-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho SONG ,  Namjoon KIM ,  Sehwan LEE ,  Deokjin JOO

IPC: G06N3/08 ,  G06F7/74 ,  G06N20/00

CPC classification number: G06N3/08 ,  G06F7/74 ,  G06N20/00

Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.