公开(公告)号：US20250077182A1

公开(公告)日：2025-03-06

申请号：US18953922

申请日：2024-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook SONG ,  Daekyeung KIM ,  Junseok PARK ,  Joonho SONG ,  Sehwan LEE ,  Junwoo JANG ,  Yunkyo CHO

IPC: G06F7/544 ,  G06N3/063

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

公开(公告)号：US20240303837A1

公开(公告)日：2024-09-12

申请号：US18663438

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan LEE

IPC: G06T7/33 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T1/20

CPC classification number: G06T7/33 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T1/20 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2210/52

Abstract: A neural network apparatus includes one or more processors comprising: a controller configured to determine a shared operand to be shared in parallelized operations as being either one of a pixel value among pixel values of an input feature map and a weight value among weight values of a kernel, based on either one or both of a feature of the input feature map and a feature of the kernel; and one or more processing units configured to perform the parallelized operations based on the determined shared operand.

公开(公告)号：US20230252298A1

公开(公告)日：2023-08-10

申请号：US18304574

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho SONG ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/08 ,  G06F17/15 ,  G06N3/045 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06F17/153 ,  G06N3/045 ,  G06N3/04

Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.

公开(公告)号：US20220335284A1

公开(公告)日：2022-10-20

申请号：US17848007

申请日：2022-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namjoon KIM ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A neural network apparatus includes a plurality of node buffers connected to a node lane and configured to store input node data by a predetermined bit size; a plurality of weight buffers connected to a weight lane and configured to store weights; and one or more processors configured to: generate first and second split data by splitting the input node data by the predetermined bit size, store the first and second split data in the node buffers, output the first split data to an operation circuit for a neural network operation on an index-by-index basis, shift the second split data, and output the second split data to the operation circuit on the index-by-index basis.

公开(公告)号：US20210027151A1

公开(公告)日：2021-01-28

申请号：US16935500

申请日：2020-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pramod Parameshwara UDUPA ,  Kiran Kolar CHANDRASEKHARAN ,  Sehwan LEE

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A processor-implemented method for generating Output Feature Map (OFM) channels using a Convolutional Neural Network (CNN), include a plurality of kernels, includes generating at least one encoded Similar or Identical Inter-Kernel Weight (S/I-IKW) stream, converting, similar and identical weights in the at least one non-pivot kernel to zero to introduce sparsity into the at least one non-pivot kernel, broadcasting at least one value to the at least one non-pivot kernel, and generating at least one OFM channel by accumulating an at least one previous OFM value with any one or any combination of any two or more of a convolution of non-zero weights of the pivot kernel and pixels of the Input Feature Map (IFM), the at least one broadcasted value, and a convolution of non-zero weights of the at least one non-pivot kernel and pixels of the IFM.

公开(公告)号：US20220284274A1

公开(公告)日：2022-09-08

申请号：US17376516

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Woo JANG ,  Jinook SONG ,  Sehwan LEE

IPC: G06N3/063 ,  G06N3/04

Abstract: A neural processing device includes a first memory configured to store universal data, a second memory distinguished from the first memory and having a capacity less than that of the first memory, a bandwidth control path configured to reconfigure a memory bandwidth for memory clients to use one of the first memory and the second memory based on a control signal, and a control logic configured to calculate a target capacity for data of a target client of the memory clients determined based on a layer configuration of an artificial neural network, and generate the control signal to store the data of the target client in the second memory based on a result of comparing the target capacity and the capacity of the second memory.

公开(公告)号：US20210263738A1

公开(公告)日：2021-08-26

申请号：US17186161

申请日：2021-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arnab ROY ,  Kiran Kolar CHANDRASEKHARAN ,  Sehwan LEE

IPC: G06F9/30

Abstract: A method for performing a pooling operation in bitwise manner, the method includes performing a pooling operation on ternary data upon receiving an input ternary vector, receiving an input binary vector, providing a fused hardware for performing the pooling operation on any of the received binary and the ternary data, and executing the pooling operation performed bitwise through the fused hardware.

公开(公告)号：US20210174179A1

公开(公告)日：2021-06-10

申请号：US16989391

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook SONG ,  Daekyeung KIM ,  Junseok PARK ,  Joonho SONG ,  Sehwan LEE ,  Junwoo JANG ,  Yunkyo CHO

IPC: G06N3/063 ,  G06F7/485

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

公开(公告)号：US20200293858A1

公开(公告)日：2020-09-17

申请号：US16816861

申请日：2020-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saptarsi DAS ,  Sabitha KUSUMA ,  Sehwan LEE ,  Ankur DESHWAL ,  Kiran Kolar CHANDRASEKHARAN

IPC: G06N3/04 ,  G06F17/16

Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.

公开(公告)号：US20190171930A1

公开(公告)日：2019-06-06

申请号：US16158660

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan LEE ,  Namjoon KIM ,  Joonho SONG ,  Junwoo JANG

IPC: G06N3/063 ,  G06F17/15 ,  G06N3/04

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network, the method includes determining operands from input feature maps and kernels, on which a convolution operation is to be performed, dispatching operand pairs combined from the determined operands to multipliers in a convolution operator, generating outputs by performing addition and accumulation operations with respect to results of multiplication operations, and obtaining pixel values of output feature maps corresponding to a result of the convolution operation based on the generated outputs.