公开(公告)号：US20140192097A1

公开(公告)日：2014-07-10

申请号：US14151427

申请日：2014-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hoon BAEK ,  Jae-Youl LEE ,  Han-Su PAE ,  Dong-Myung LEE ,  Sun-Ik LEE ,  Yong-Min CHOI

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2330/026 ,  G09G2330/06 ,  G09G2370/08

Abstract: A display driver circuit includes a source driver and a display driver. The source driver drives source lines of a display panel, and the timing controller transmits image data to the source driver and controls the source driver such that the transmitted image data is displayed in the display panel. The timing controller randomizes the image data in a scrambling mode when the timing controller transmits data packets including pixel data field in which the image data is written.

Abstract translation: 显示驱动器电路包括源极驱动器和显示驱动器。 源驱动器驱动显示面板的源极线，定时控制器将图像数据发送到源驱动器并控制源驱动器，使得发送的图像数据被显示在显示面板中。 当定时控制器发送包括其中写入图像数据的像素数据字段的数据分组时，定时控制器以加扰模式随机化图像数据。

公开(公告)号：US20170116954A1

公开(公告)日：2017-04-27

申请号：US15271837

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon BAEK ,  Hyunwook LIM ,  Kwi Sung YOO ,  Eun-Young JIN ,  Kyongho KIM ,  JaeYoul LEE ,  Youngmin CHOI

IPC: G09G5/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/08 ,  H03L7/099

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2310/027 ,  G09G2330/10 ,  G09G2370/10 ,  G09G2370/16 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/095

Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.