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公开(公告)号：US20220407949A1
公开(公告)日：2022-12-22
申请号：US17679412
申请日：2022-02-24
发明人： Yong-Yun PARK , Kyungho RYU , Kilhoon LEE , Hyunwook LIM , Youngmin CHOI , Kyungae KIM
IPC分类号： H04L69/324
摘要： Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.
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公开(公告)号：US20220189364A1
公开(公告)日：2022-06-16
申请号：US17412965
申请日：2021-08-26
发明人： Jinyong PARK , Hongki KWON , Taewoo KIM , Yonghoon YU , Hyunwook LIM , Byeongcheol JANG , Woohyuk JANG , Hojun CHUNG
摘要： A display driver circuit receives externally-encoded image data and processes the data using a memory (graphic RAM), an internal encoder, and an external decoder configured to operate on the externally-encoded image data. The processed data is provided to a display device by a source driver of the display driver circuit. Data is processed through the graphic RAM and an internal decoder or the external decoder depending on whether a slice of the data is a currently received update slice, a recently received standby slice, or a still slice.
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3.发明公开公开(公告)号：US20240185764A1
公开(公告)日：2024-06-06
申请号：US18523354
申请日：2023-11-29
发明人： Taekon YU , Jonghee NA , Sewhan NA , Hyeonsu PARK , Hyunwook LIM
IPC分类号： G09G3/20 , G09G3/3225
CPC分类号： G09G3/2096 , G09G3/3225 , G09G2300/0819 , G09G2300/0842 , G09G2310/08 , G09G2320/0209 , G09G2320/045 , G09G2340/00
摘要： A display driving circuit includes: a compensation control circuit configured to: generate a compensation voltage based on input image data and information of a display panel operatively connected to the display driving circuit, and compensate a data voltage of the input image data based on the compensation voltage; and a timing control circuit configured to output the compensated data voltage to a plurality of pixels in the display panel.
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公开(公告)号：US20230246801A1
公开(公告)日：2023-08-03
申请号：US18192742
申请日：2023-03-30
发明人： Jungpil LIM , Kyungho RYU , Kilhoon LEE , Hyunwook LIM
CPC分类号： H04L7/0033 , H04L7/0087 , H03L7/102 , H03L7/099 , H03L7/0891 , H03L7/113
摘要： A display device including: a timing controller outputting a reference dock signal and a data packet, wherein the data packet includes a dock signal embedded in a data signal; a dock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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公开(公告)号：US20230134597A1
公开(公告)日：2023-05-04
申请号：US17747521
申请日：2022-05-18
发明人： Sewhan NA , Jiheon OK , Unki PARK , Jaeyoul LEE , Hyunwook LIM
摘要： A display device includes a display panel, a touch sensor, a display driver and a touch controller. The display driver drives the display panel based on input image data, and generates predicted noise data corresponding to the input image data by using an artificial neural network. The touch controller receives a touch sensing signal from the touch sensor by driving the touch sensor, converts the touch sensing signal that is an analog signal into touch sensing data that are digital data, and compensates the touch sensing data based on the predicted noise data.
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公开(公告)号：US20220028341A1
公开(公告)日：2022-01-27
申请号：US17492985
申请日：2021-10-04
发明人： Unki PARK , Minsik KIM , Hyeonsu PARK , Hyunwook LIM , Woohyuk JANG
IPC分类号： G09G3/3258
摘要： A display driving circuit for driving a display panel includes a control logic that adjusts brightness of a first partial area by adjusting pixel data values included in partial image data to be displayed on the first partial area of the display panel based on received brightness control information, and a data driver that generates image signals by digital-analog conversion of pixel data values provided from the control logic, the data driver providing the image signals to the display panel.
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公开(公告)号：US20230378963A1
公开(公告)日：2023-11-23
申请号：US18074775
申请日：2022-12-05
发明人： Kyungho RYU , Yongil KWON , Kilhoon LEE , Jung-Pil LIM , Hyunwook LIM
CPC分类号： H03L7/091 , H04L7/033 , H04L7/0037 , H04L7/0087 , G06F1/10 , G11C7/222
摘要： The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.
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公开(公告)号：US20230154437A1
公开(公告)日：2023-05-18
申请号：US18151064
申请日：2023-01-06
发明人： Unki PARK , Se Whan NA , Hyunwook LIM , Woohyuk JANG
CPC分类号： G09G5/10 , H04N23/57 , G09G2300/0439 , G09G2310/0232 , G09G2320/0233
摘要： An electronic device includes a display panel that includes a first region including first pixel groups and a second region including second pixel groups, and a compensation circuit. The compensation circuit may receive first image data. The compensation circuit may compensate to generate second image data in response to a determination that the first image data corresponds to at least one of one or more particular first pixel groups that are adjacent to a boundary between the first region and the second region or one or more particular second pixel groups that are adjacent to the boundary. The compensation circuit outputs the second image data to the display panel.
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9.发明公开公开(公告)号：US20230143912A1
公开(公告)日：2023-05-11
申请号：US17985599
申请日：2022-11-11
发明人： Kyungho RYU , Kyongho KIM , Yongyun PARK , Kilhoon LEE , Yeongcheol RHEE , Taeho LEE , Hyunwook LIM
IPC分类号： G09G5/00
CPC分类号： G09G5/008 , G09G2370/04
摘要： Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.
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公开(公告)号：US20220006604A1
公开(公告)日：2022-01-06
申请号：US17476782
申请日：2021-09-16
发明人： Jungpil LIM , Kyungho RYU , Kilhoon LEE , Hyunwook LIM
摘要： A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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