公开(公告)号：US20250149105A1

公开(公告)日：2025-05-08

申请号：US18648882

申请日：2024-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun LEE ,  Sang-Hyo KIM ,  Heeju NA ,  Myungkyu LEE ,  Sunghye CHO ,  Donghyun KONG ,  Kyomin SOHN

IPC: G11C29/42

Abstract: A memory device according to various example embodiments includes a memory cell array having a plurality of memory cells connected to word lines and bit lines; and an error correction circuit configured to perform error correction on data read from the memory cell array, wherein the error correction circuit is configured to perform at least one of a 1-bit error correction operation, a 2-bit error detection operation, or a 3-bit error detection operation using a parity check matrix, and the parity check matrix is configured so that columns are arranged in an order of odd-odd-even degree, and leading one (LO) of each row is arranged in a stepped structure.