公开(公告)号：US20240232012A1

公开(公告)日：2024-07-11

申请号：US18399864

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongmuk KANG ,  KYUNG-HO LEE ,  MYUNGKYU LEE ,  KI-HEUNG KIM ,  KYOMIN SOHN ,  KIJUN LEE ,  SUNGHYE CHO ,  HYONGRYOL HWANG

IPC: G06F11/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C29/42

CPC classification number: G06F11/1068 ,  G11C7/06 ,  G11C7/1078 ,  G11C7/12 ,  G11C29/42

Abstract: A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.