公开(公告)号：US10892185B2

公开(公告)日：2021-01-12

申请号：US16511019

申请日：2019-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun Park ,  Haewang Lee ,  Jaemyung Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A semiconductor device including a first interconnection line having a first end and extending in a first direction; a first blocking pattern at the first end of the first interconnection line and adjacent to the first interconnection line in the first direction; a second interconnection line spaced apart from the first interconnection line in a second direction crossing the first direction and extending in the first direction, the second interconnection line having a second end; and a second blocking pattern at the second end of the second interconnection line and adjacent to the second interconnection line in the first direction, wherein a width of the first blocking pattern in the first direction is different from a width of the second blocking pattern in the first direction.

公开(公告)号：US10403619B2

公开(公告)日：2019-09-03

申请号：US15787244

申请日：2017-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung-Sung Kim ,  Chul-Hong Park ,  Haewang Lee

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0948 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

公开(公告)号：US11551978B2

公开(公告)日：2023-01-10

申请号：US17089822

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Jaeseok Yang ,  Haewang Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

公开(公告)号：US10861747B2

公开(公告)日：2020-12-08

申请号：US16439860

申请日：2019-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Jaeseok Yang ,  Haewang Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.