公开(公告)号：US10403619B2

公开(公告)日：2019-09-03

申请号：US15787244

申请日：2017-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung-Sung Kim ,  Chul-Hong Park ,  Haewang Lee

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0948 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

公开(公告)号：US10402528B2

公开(公告)日：2019-09-03

申请号：US14966264

申请日：2015-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US10170421B2

公开(公告)日：2019-01-01

申请号：US15647467

申请日：2017-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta Rwik ,  Su-Hyeon Kim ,  Chul-Hong Park ,  Jae-Hyoung Lim

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

公开(公告)号：US09425148B2

公开(公告)日：2016-08-23

申请号：US13718138

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Kim ,  Hae-Wang Lee ,  Chul-Hong Park ,  Dong-Kyun Sohn ,  Jong-Shik Yoon

IPC: H01L23/538 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.

Abstract translation: 半导体器件及其制造方法包括在衬底上的层间电介质膜图案，层间电介质膜图案内的第一布线，并且具有第一方向的第一长度，层间电介质膜图案内的第二布线和 与第一布线分离，以及与第一布线和第二布线接触的间隔件。 间隔件将第一布线和第二布线彼此电分离。 第二布线具有与第一方向上的第一长度不同的第二长度。

公开(公告)号：US09230053B2

公开(公告)日：2016-01-05

申请号：US14533553

申请日：2014-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jong Lee ,  Chul-Hong Park ,  Roo-Li Choi ,  Duck-Hyung Hur

IPC: G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027

Abstract: A design rule generating method is provided. The method includes receiving a test pattern, providing a plurality of workflows, which correspond to the test pattern and are preset in relation to a lithography model and a mask generation method, and performing simulation on the test pattern according to a workflow selected from the workflows.

Abstract translation: 提供了一种设计规则生成方法。 该方法包括接收测试图案，提供对应于测试图案并相对于光刻模型和掩模生成方法预设的多个工作流程，以及根据从工作流程中选择的工作流程在测试图案上执行模拟 。

公开(公告)号：US11461521B2

公开(公告)日：2022-10-04

申请号：US16401820

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sidharth Rastogi ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: G06F30/327 ,  H01L27/02 ,  G06F30/398

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

公开(公告)号：US11935835B2

公开(公告)日：2024-03-19

申请号：US17120616

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/823481

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US10121735B2

公开(公告)日：2018-11-06

申请号：US15794131

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon-Ah Nam ,  Ikuo Nakamatsu ,  Dong-Hyun Kim ,  Chul-Hong Park ,  Yun-Se Oh ,  Hae-Wang Lee ,  Ho-Jun Choi

IPC: H01L27/088 ,  H01L23/498 ,  H01L23/48 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes active fins on a substrate. Gate lines each extend in the second direction on the active fins. A contact plug is positioned on the active fins. A first via is in one of the first contact plugs. A first conductive line overlaps a first via. A first distance from a first active fin on which a first gate line of the gate lines is formed to an end of the first gate line is more than a predetermined distance. A second distance from a second active fin on which the first gate line is formed to the first active fin of the active fins is equal to or less than the predetermined distance. The second active fin is spaced apart from the first contact plugs to not overlap the first contact plugs.

公开(公告)号：US09965579B2

公开(公告)日：2018-05-08

申请号：US14690227

申请日：2015-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Sang-Hoon Baek ,  Su-Hyeon Kim ,  Kyoung-Yun Baek ,  Sung-Wook Ahn ,  Sang-Kyu Oh ,  Seung-Jae Jung

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

公开(公告)号：US09741661B2

公开(公告)日：2017-08-22

申请号：US15188743

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Sengupta Rwik ,  Su-Hyeon Kim ,  Chul-Hong Park ,  Jae-Hyoung Lim

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.