公开(公告)号：US20190207008A1

公开(公告)日：2019-07-04

申请号：US16294158

申请日：2019-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Kyung Ho KIM ,  Dong Suk SHIN

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L27/11 ,  H01L27/088

CPC classification number: H01L29/4983 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.

公开(公告)号：US20180358358A1

公开(公告)日：2018-12-13

申请号：US15801797

申请日：2017-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Kwan YU ,  Won Hyung KANG ,  Hyo Jin KIM ,  Sung Bu MIN

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/36 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7853

Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.

公开(公告)号：US20220130982A1

公开(公告)日：2022-04-28

申请号：US17571694

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Seung Hun LEE ,  Yang XU

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/201 ,  H01L29/20

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US20180342583A1

公开(公告)日：2018-11-29

申请号：US15800483

申请日：2017-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Hyo Jin KIM ,  Ryong HA

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/76224 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/7848 ,  H01L29/7854

Abstract: A semiconductor device is provided. The semiconductor device includes a fin-type pattern formed on a substrate and including first and second sidewalls, which are defined by a trench, a field insulating film placed in contact with the first and second sidewalls and filling the trench, and an epitaxial pattern formed on the fin-type pattern and including a first epitaxial layer and a second epitaxial layer, which is formed on the first epitaxial layer.

公开(公告)号：US20170345911A1

公开(公告)日：2017-11-30

申请号：US15479459

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Kyung Ho KIM ,  Dong Suk SHIN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/4983 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.