公开(公告)号：US20240379639A1

公开(公告)日：2024-11-14

申请号：US18397837

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Joo Park ,  Hyung Jun Jeon ,  Pil-Kyu Kang

IPC: H01L25/16 ,  H01L23/498 ,  H10B80/00

Abstract: An example semiconductor package includes a structure, a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure, a dummy semiconductor chip disposed on and contacting the upper surface of the structure, a molding layer surrounding a sidewall of the first semiconductor chip and a sidewall of the dummy semiconductor chip on the upper surface of the structure, a redistribution layer disposed on an upper surface of the first semiconductor chip, an upper surface of the dummy semiconductor chip, and an upper surface of the molding layer, a first through-via extending through the molding layer in a vertical direction and electrically connecting the structure and the redistribution layer, a second through-via extending through the dummy semiconductor chip in the vertical direction and electrically connecting the structure and the redistribution layer, and a capacitor disposed inside the dummy semiconductor chip.

公开(公告)号：US12266609B2

公开(公告)日：2025-04-01

申请号：US17680808

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Jun Jeon ,  Kwang Jin Moon ,  Son-Kwan Hwang

IPC: H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip, which includes a first semiconductor substrate and a first bonding layer on the first semiconductor substrate. A second semiconductor chip includes a second semiconductor substrate, a second bonding layer bonded to the first bonding layer, and a chip-through-via which penetrates the second semiconductor substrate and is connected to the second bonding layer. A passivation film extends along an upper side of the second semiconductor chip and does not extend along side-faces of the second semiconductor chip. The chip-through-via penetrates the passivation film. A multiple-gap-fill film extends along the upper side of the first semiconductor chip, the side faces of the second semiconductor chip, and the side faces of the passivation film. The multiple-gap-fill films includes an inorganic filling film and an organic filling film which are sequentially stacked on the first semiconductor chip.

公开(公告)号：US20200373186A1

公开(公告)日：2020-11-26

申请号：US16703062

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoe Chul Kim ,  Seok Ho Kim ,  Tae Yeong Kim ,  Hoon Joo Na ,  Hyung Jun Jeon

IPC: H01L21/683 ,  H01L21/677 ,  H01L23/00

Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.

公开(公告)号：US11728200B2

公开(公告)日：2023-08-15

申请号：US16703062

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoe Chul Kim ,  Seok Ho Kim ,  Tae Yeong Kim ,  Hoon Joo Na ,  Hyung Jun Jeon

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/677

CPC classification number: H01L21/6836 ,  H01L21/67757 ,  H01L24/94

Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.