公开(公告)号：US12170259B2

公开(公告)日：2024-12-17

申请号：US17715103

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Bin Seo ,  Seok Ho Kim ,  Kwang Jin Moon

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

公开(公告)号：US20200168471A1

公开(公告)日：2020-05-28

申请号：US16439211

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOO HEE JANG ,  Seok Ho Kim ,  Hoon Joo NA ,  Kwang Jin Moon ,  Jae Hyung Park ,  Kyu Ha Lee

IPC: H01L21/321 ,  H01L27/146

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region

公开(公告)号：US20240006362A1

公开(公告)日：2024-01-04

申请号：US18155988

申请日：2023-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Bin Seo ,  Seok Ho Kim ,  Kwang Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/14519 ,  H01L2224/1403 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/13083 ,  H01L2224/05655 ,  H01L2224/13155 ,  H01L2224/13147 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13144

Abstract: A semiconductor device including a substrate, a wiring pattern in the substrate, a passivation layer on the substrate, the passivation layer and the substrate including a first recess penetrating a part of each of the passivation layer and the substrate and extending toward the wiring pattern, a post connected to the wiring pattern and including a first portion within the first recess and a second portion on the first portion and protruding from a top surface of the passivation layer, a signal bump including a seed layer on the post, a lower bump on the seed layer, and an upper bump on the lower bump, and a heat transfer bump apart from the signal bump, electrically insulated from the wiring pattern, and including another seed layer on the passivation layer, another lower bump on the another seed layer, and another upper bump on the another lower bump may be provided.

公开(公告)号：US11728200B2

公开(公告)日：2023-08-15

申请号：US16703062

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoe Chul Kim ,  Seok Ho Kim ,  Tae Yeong Kim ,  Hoon Joo Na ,  Hyung Jun Jeon

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/677

CPC classification number: H01L21/6836 ,  H01L21/67757 ,  H01L24/94

Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.

公开(公告)号：US20180138164A1

公开(公告)日：2018-05-17

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/67 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US11417536B2

公开(公告)日：2022-08-16

申请号：US16439211

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo Hee Jang ,  Seok Ho Kim ,  Hoon Joo Na ,  Kwang Jin Moon ,  Jae Hyung Park ,  Kyu Ha Lee

IPC: H01L21/321 ,  H01L27/146 ,  H01L23/00

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.

公开(公告)号：US20200373186A1

公开(公告)日：2020-11-26

申请号：US16703062

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoe Chul Kim ,  Seok Ho Kim ,  Tae Yeong Kim ,  Hoon Joo Na ,  Hyung Jun Jeon

IPC: H01L21/683 ,  H01L21/677 ,  H01L23/00

Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.

公开(公告)号：US10770447B2

公开(公告)日：2020-09-08

申请号：US16400465

申请日：2019-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin Lee ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/67

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US10468400B2

公开(公告)日：2019-11-05

申请号：US15869808

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil Kyu Kang ,  Seok Ho Kim ,  Tae Yeong Kim ,  Kwang Jin Moon ,  Ho Jin Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L21/18 ,  H01L23/00

Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.

公开(公告)号：US10325897B2

公开(公告)日：2019-06-18

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin Lee ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.