公开(公告)号：US10177149B2

公开(公告)日：2019-01-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk Chai ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US11417536B2

公开(公告)日：2022-08-16

申请号：US16439211

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo Hee Jang ,  Seok Ho Kim ,  Hoon Joo Na ,  Kwang Jin Moon ,  Jae Hyung Park ,  Kyu Ha Lee

IPC: H01L21/321 ,  H01L27/146 ,  H01L23/00

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.

公开(公告)号：US20200373186A1

公开(公告)日：2020-11-26

申请号：US16703062

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoe Chul Kim ,  Seok Ho Kim ,  Tae Yeong Kim ,  Hoon Joo Na ,  Hyung Jun Jeon

IPC: H01L21/683 ,  H01L21/677 ,  H01L23/00

Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.

公开(公告)号：US12148784B2

公开(公告)日：2024-11-19

申请号：US17393855

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Shik Kim ,  Min-Sun Keel ,  Hoon Joo Na ,  Kang Ho Lee ,  Kil Ho Lee ,  Sang Kil Lee ,  Jung Hyuk Lee ,  Shin Hee Han

IPC: H01L21/768 ,  H01L27/146

Abstract: An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures.

公开(公告)号：US20200243466A1

公开(公告)日：2020-07-30

申请号：US16527323

申请日：2019-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Nam Kim ,  Tae Seong Kim ,  Hoon Joo Na ,  Kwang Jin Moon

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.

公开(公告)号：US20220375983A1

公开(公告)日：2022-11-24

申请号：US17573826

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Kuk Kang ,  Min Ho Jang ,  Hoon Joo Na ,  Hee Ju Shin

IPC: H01L27/146

Abstract: An image sensor is provided. The image sensor includes unit pixels inside the substrate; a pixel separation pattern provided between the unit pixels, inside the substrate; a first inter-wiring insulating film provided on the first surface of the substrate; a pad pattern provided inside the first inter-wiring insulating film; a first connection pattern provided inside the first inter-wiring insulating film, an upper surface of the first connection pattern and an upper surface of the first inter-wiring insulating film being provided along a first common plane; a second inter-wiring insulating film provided on the upper surface of the first inter-wiring insulating film; a second connection pattern provided inside the second inter-wiring insulating film, a lower surface of the second connection pattern and a lower surface of the second inter-wiring insulating film being provided along a second common plane; and a microlens provided on the second surface of the substrate. The first connection pattern is provided in an island shape from a planar viewpoint.

公开(公告)号：US10600913B2

公开(公告)日：2020-03-24

申请号：US16100804

申请日：2018-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun Chung ,  Jong Ho Park ,  Seung Ha Oh ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/283 ,  H01L21/324

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

公开(公告)号：US11967595B2

公开(公告)日：2024-04-23

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk Chai ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L27/092 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US11728200B2

公开(公告)日：2023-08-15

申请号：US16703062

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoe Chul Kim ,  Seok Ho Kim ,  Tae Yeong Kim ,  Hoon Joo Na ,  Hyung Jun Jeon

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/677

CPC classification number: H01L21/6836 ,  H01L21/67757 ,  H01L24/94

Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.

公开(公告)号：US11133277B2

公开(公告)日：2021-09-28

申请号：US16527323

申请日：2019-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Nam Kim ,  Tae Seong Kim ,  Hoon Joo Na ,  Kwang Jin Moon

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.